參數(shù)資料
型號： 28233-11
廠商： CONEXANT SYSTEMS
元件分類： 數(shù)字傳輸電路
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： TRANSCEIVER, PQFP160
封裝： PLASTIC, MQFP-160
文件頁數(shù)： 141/161頁
文件大?。?/td> 1832K
代理商： 28233-11
CN8223
4.0 Electrical and Mechanical Specifications
ATM Transmitter/Receiver with UTOPIA Interface
4.3 Timing
100046C
Conexant
4-7
Figure 4-2. Line Interface Timing
—
DS1, E1, DS3, E3 External Framers
TXCKI,TXCKIHS
TXSYI
TXDATO (DS1/E1)
10
14
9
12
13
11
8
5
2
3
6
7
4
1
TXDATO (DS3/E3)
RXCKI,RXCKIHS
RXSYI
RXDATI
8
Table 4-4. Line Interface Timing
—
Internal Framers
Name
Interval
Description
Min
Max
ttxcki
1
–
6
Transmit Clock Period
(1)
6.4
—
ttxh
1
–
5
Transmit Clock Pulse Width High
(2)
2.9
—
tcico
1
–
2
Transmit Clock In to Clock Out Delay (non-inverted)
2.6
10.0
tcod
2
–
3
Transmit Clock Out to Transmit Data Out
1.0
4.0
tcopn
2
–
4
Transmit Clock Out to Transmit Pos/Neg Out
0.1
1.0
trxcki
7
–
11
Receive Clock Period
6.4
—
trxh
7
–
10
Receive Clock Pulse Width High
(2)
2.9
—
trdck
8
–
10
Receive Data Setup to Receive Clock Falling Edge
1.0
—
tckrd
10
–
12
Receive Data Hold after Receive Clock Falling Edge
0.8
—
tpnck
9
–
10
Receive Pos/Neg Setup to Receive Clock Falling Edge
0
—
tckpn
10
–
13
Receive Pos/Neg Hold after Receive Clock Falling Edge
3.5
—
NOTE(S):
-
(1)
Nominal clock periods are: E3
–
29.1 ns STS-3c
–
6.4 ns
STS-1
–
19.3 ns
E4
–
7.2 ns
D3
–
22.4 ns
(2)
Duty cycle must be 45/55 at maximum input clock rate.
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