參數(shù)資料
型號： 28233-11
廠商： CONEXANT SYSTEMS
元件分類： 數(shù)字傳輸電路
英文描述： ATM Transmitter/Receiver with UTOPIA Interface
中文描述： TRANSCEIVER, PQFP160
封裝： PLASTIC, MQFP-160
文件頁數(shù)： 140/161頁
文件大?。?/td> 1832K
代理商： 28233-11
4.0 Electrical and Mechanical Specifications
CN8223
4.3 Timing
ATM Transmitter/Receiver with UTOPIA Interface
4-6
Conexant
100046C
4.3.2 Line Interface Timing
Tables 4-3
through
4-6
and
Figures 4-2
through
4-5
display the timing
requirements and characteristics of the line interfaces and parallel data and
overhead ports. All times are in nanoseconds. Example LIU circuits are provided
in CN8223 EVM schematics.
Table 4-3. Line Interface Timing
—
DS1, E1, DS3, E3 External Framers
Name
Interval
Description
Min
Max
ttxcki
1
–
7
Transmit Clock Period
(1)
22
—
ttxh
1
–
4
Transmit Clock Pulse Width High
(2)
8.8
—
ttsck
3
–
4
Transmit Sync Setup to Transmit Clock Falling Edge
0
—
tckts
4
–
6
Transmit Sync Hold after Transmit Clock Falling Edge
2.4
—
tckd1
1
–
2
Transmit Clock Rising Edge to DS1/E1 Serial Data Out
2.9
12.2
tckd2
4
–
5
Transmit Clock Falling Edge to DS3/E3 Serial Data Out
2.9
10.4
trxcki
8
–
13
Receive Clock Period
22
—
trxh
8
–
11
Receive Clock Pulse Width High
(2)
8.8
15
trsck
9
–
11
Receive Sync Setup to Receive Clock Falling Edge
0
—
tckrs
11
–
12
Receive Sync Hold after Receive Clock Falling Edge
3.4
—
trdck
10
–
11
Receive Data Setup to Receive Clock Falling Edge
2.3
—
tckdr
11
–
14
Receive Data Hold after Receive Clock Falling Edge
2.6
—
NOTE(S):
(1)
Nominal clock periods are:
DS1
–
648 ns
E1
–
488 ns
E3
–
29.1 ns
DS3
–
22.4 ns
(2)
Duty cycle must be 40/60 at maximum input clock rate.
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