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參數(shù)資料
| 型號： | 27C2001 |
| 廠商： | 意法半導(dǎo)體 |
| 英文描述： | 2 Mbit 256Kb x 8 UV EPROM and OTP EPROM |
| 中文描述： | 2兆位的256Kb × 8紫外線存儲器和OTP存儲器 |
| 文件頁數(shù)： | 5/17頁 |
| 文件大?。?/td> | 114K |
| 代理商： | 27C2001 |
5/17
M27C2001
Table 7. Read Mode DC Characteristics
(1)
(TA = 0 to 70
°
C or –40 to 85
°
C; V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Symbol
Parameter
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Maximum DC voltage on Output is V
CC
+0.5V.
Table 8A. Read Mode AC Characteristics
(1)
(TA = 0 to 70
°
C or –40 to 85
°
C; V
CC
= 5V
±
5% or 5V
±
10%; V
PP
= V
CC
)
Note: 1. V
CC
must be applied simultaneously with or before V
PP
and removed simultaneously or after V
PP
.
2. Sampled only, not 100% tested.
3. In case of 45ns speed see High Speed AC measurement conditions.
Test Condition
Min
Max
Unit
I
LI
Input Leakage Current
0V
≤
V
IN
≤
V
CC
±
10
μ
A
I
LO
Output Leakage Current
0V
≤
V
OUT
≤
V
CC
±
10
μ
A
I
CC
Supply Current
E = V
IL
, G = V
IL
,
I
OUT
= 0mA, f = 5MHz
30
mA
I
CC1
Supply Current (Standby) TTL
E = V
IH
1
mA
I
CC2
Supply Current (Standby) CMOS
E > V
CC
– 0.2V
100
μ
A
I
PP
Program Current
V
PP
= V
CC
10
μ
A
V
IL
Input Low Voltage
–0.3
0.8
V
V
IH(2)
Input High Voltage
2
V
CC
+ 1
V
V
OL
Output Low Voltage
I
OL
= 2.1mA
0.4
V
V
OH
Output High Voltage TTL
I
OH
= –400
μ
A
2.4
V
Output High Voltage CMOS
I
OH
= –100
μ
A
V
CC
– 0.7V
V
Symbol
Alt
Parameter
Test Condition
M27C2001
Unit
-55
(3)
-70
-80
-90
Min
Max
Min
Max
Min
Max
Min
Max
t
AVQV
t
ACC
Address Valid to
Output Valid
E = V
IL
, G = V
IL
55
70
80
90
ns
t
ELQV
t
CE
Chip Enable Low to
Output Valid
G = V
IL
55
70
80
90
ns
t
GLQV
t
OE
Output Enable Low
to Output Valid
E = V
IL
30
35
40
40
ns
t
EHQZ(2)
t
DF
Chip Enable High to
Output Hi-Z
G = V
IL
0
30
0
30
0
30
0
30
ns
t
GHQZ(2)
t
DF
Output Enable High
to Output Hi-Z
E = V
IL
0
30
0
30
0
30
0
30
ns
t
AXQX
t
OH
Address Transitionto
Output Transition
E = V
IL
, G = V
IL
0
0
0
0
ns
Two Line Output Control
Because EPROMs are usually used in larger
memory arrays, this product features a 2 line con-
trol function which accommodates the use of mul-
tiple memory connection. The two line control
function allows:
a. the lowest possible memory power dissipation,
b. complete assurance that output bus contention
will not occur.
For the most efficient use of these two control
lines, Eshould be decoded and used as theprima-
ry device selecting function, while G should be
made a common connection to all devices in the
array and connected to the READ line from the
system control bus. Thisensures that all deselect-
ed memory devices are in their lowpower standby
mode and that the output pins are only active
when data is required from a particular memory
device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| 27C2001-10F1 | 制造商:STMicroelectronics 功能描述: |
| 27C2048 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:2 Megabit (128k X 16-Bit) CMOS EPROM(173.55 k) |
| 27C210 | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:1M (64K x 16) CHMOS EPROM |
| 27C2100-12 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128x16] CMOS EPROM |
| 27C2100-15 | 制造商:MCNIX 制造商全稱:Macronix International 功能描述:2M-BIT [256Kx8/128x16] CMOS EPROM |
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