參數(shù)資料
型號: 256MBDDRSDRAM
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: DDR SDRAM Specification Version 0.3
中文描述: DDR SDRAM的規(guī)格版本0.3
文件頁數(shù): 8/51頁
文件大?。?/td> 658K
代理商: 256MBDDRSDRAM
- 8 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
1. Key Features
Preliminary
Double-data-rate architecture; two data transfers per clock cycle
Bidirectional data strobe(DQS)
Four banks operation
Differential clock inputs(CK and CK)
DLL aligns DQ and DQS transition with CK transition
MRS cycle with address key programs
-. Read latency 2, 2.5 (clock)
-. Burst length (2, 4, 8)
-. Burst type (sequential & interleave)
All inputs except data & DM are sampled at the positive going edge of the system clock(CK)
Data I/O transactions on both edges of data strobe
Edge aligned data output, center aligned data input
LDM,UDM/DM for write masking only
Auto & Self refresh
7.8us refresh interval(8K/64ms refresh)
Maximum burst refresh cycle : 8
66pin TSOP II package
1.1 Features
1.2 Operating Frequencies
*CL : Cas Latency
Table 1. Operating frequency and DLL jitter
- A2(DDR266A)
133MHz
-
±0.75ns
- B0(DDR266B)
100MHz
133MHz
±0.75ns
- A0(DDR200)
100MHz
-
±0.8ns
Speed @CL2
Speed @CL2.5
DLL jitter
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