參數(shù)資料
型號： 256MBDDRSDRAM
廠商： SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述： DDR SDRAM Specification Version 0.3
中文描述： DDR SDRAM的規(guī)格版本0.3
文件頁數(shù)： 38/51頁
文件大?。?/td> 658K
代理商： 256MBDDRSDRAM
- 38 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
7.2 DDR SDRAM SPEC Items and Test Conditions
Preliminary
Typical case: VDD = 2.5V, T = 25’C
Worst case : VDD = 2.7V, T = 10’C
Conditions
Operating current - One bank Active-Precharge;
tRC=tRCmin;tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
DQ,DM and DQS inputs changing twice per clock cycle;
address and control inputs changing once per clock cycle
Operating current - One bank operation ;
One bank open, BL=4, Reads
- Refer to the following page for detailed test condition
Percharge power-down standby current;
All banks idle; power - down mode;
CKE = <VIL(max); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
Precharge Floating standby current;
CS# > =VIH(min);All banks idle;
CKE > = VIH(min); tCK=100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs changing once per clock cycle;
Vin = Vref for DQ,DQS and DM
Precharge Quiet standby current;
CS# > = VIH(min); All banks idle;
CKE > = VIH(min); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Address and other control inputs stable with keeping >= VIH(min) or =<VIL(max);
Vin = Vref for DQ ,DQS and DM
Active power - down standby current ;
one bank active; power-down mode;
CKE=< VIL (max); tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B;
Vin = Vref for DQ,DQS and DM
Active standby current;
CS# >= VIH(min); CKE>=VIH(min);
one bank active; active - precharge; tRC=tRASmax; tCK = 100Mhz for DDR200,
133Mhz for DDR266A & DDR266B; DQ, DQS and DM inputs changing twice
per clock cycle; address and other control inputs changing once
per clock cycle
Operating current - burst read;
Burst length = 2; reads; continguous burst;
One bank active; address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A, CL=2.5 at tCK =
133Mhz for DDR266B ; 50% of data changing at every burst; lout = 0 m A
Operating current - burst write;
Burst length = 2; writes; continuous burst;
One bank active address and control inputs changing once per clock cycle;
CL=2 at tCK = 100Mhz for DDR200, CL=2 at tCK = 133Mhz for DDR266A,
CL=2.5 at tCK = 133Mhz for DDR266B ; DQ, DM and DQS inputs changing twice
per clock cycle, 50% of input data changing at every burst
Auto refresh current;
tRC = tRFC(min) - 8*tCK for DDR200 at 100Mhz,
10*tCK for DDR266A & DDR266B at 133Mhz; distributed refresh
Self refresh current;
CKE =< 0.2V; External clock should be on;
tCK = 100Mhz for DDR200, 133Mhz for DDR266A & DDR266B
Orerating current - Four bank operation ;
Four bank interleaving with BL=4
-Refer to the following page for detailed test condition
Symbol
IDD0
Typical
-
Worst
-
IDD1
-
-
IDD2P
-
-
IDD2F
-
-
IDD2Q
-
-
IDD3P
-
-
IDD3N
-
-
IDD4R
-
-
IDD4W
-
-
IDD5
-
-
IDD6
-
-
IDD7
-
-
Table 12. DDR SDRAM spec Items and Test Conditions
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