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| 型號： | 256MBDDRSDRAM |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.3 |
| 中文描述： | DDR SDRAM的規(guī)格版本0.3 |
| 文件頁數(shù)： | 49/51頁 |
| 文件大?。?/td> | 658K |
| 代理商： | 256MBDDRSDRAM |
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- 49 -
REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
12. QFC function
when drive low on reads coincident with the start of DQS, this DRAM output signal says that one cycle later
there will be the first valid DQS output and returned to HI-Z after this finishing a burst operation. It is also
driven low shortly after a write command is received and returned to HI-Z shortly after the last data strobe
transition is received. Whenever the device is in standby, the signal is HI-Z. DQS is intended to enable an
external data switch. QFC can be enabled or disabled through EMRS control
.
QFC timing on Read operation
QFC on reads is enabled coincident with the start of DQS preamble, and disabled coincident with the end of
DQS postamble
Command
2
0
1
5
3
4
8
6
7
Read
Dout 0 Dout 1
Hi-Z
DQS
DQ’S
QFC
t
QCS
t
QCH
CL = 2, BL = 2
CK
CK
QFC definition
Figure 27. QFC timing on read operation
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