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參數(shù)資料
| 型號： | 256MBDDRSDRAM |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | DDR SDRAM Specification Version 0.3 |
| 中文描述： | DDR SDRAM的規(guī)格版本0.3 |
| 文件頁數(shù)： | 16/51頁 |
| 文件大?。?/td> | 658K |
| 代理商： | 256MBDDRSDRAM |
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REV. 0.3 November 2. 2000
256Mb DDR SDRAM
Preliminary
3.2.2.2 Extended Mode Register Set(EMRS)
Figure 7. Extend Mode Register set
The extended mode register stores the data for enabling or disabling DLL, QFC and selecting output driver
size. The default value of the extended mode register is not defined, therefore the extened mode register must
be written after power up for enabling or disabling DLL. The extended mode register is written by asserting low
on CS, RAS, CAS, WE and high on BA0(The DDR SDRAM should be in all bank precharge with CKE already
high prior to writing into the extended mode register). The state of address pins A0 ~ A11 and BA1 in the
same cycle as CS, RAS, CAS and WE going low are written in the extended mode register. Two clock cycles
are required to complete the write operation in the extended mode register. The mode register contents can
be changed using the same command and clock cycle requirements during operation as long as all banks are
in the idle state. A0 is used for DLL enable or disable. "High" on BA0 is used for EMRS. All the other address
pins except A0 and BA0 must be set to low for proper EMRS operation. Refer to the table for specific codes.
Address Bus
RFU
RFU : Must be set "0"
Extended Mode Register
DLL
BA
1
BA
0
A
11
A
10
A
9
A
8
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
1
A
0
0
1
DLL Enable
Enable
Disable
BA
0
0
1
A
n
~ A
0
(Existing)MRS Cycle
Extended Funtions(EMRS)
QFC control
Disable(Default)
Enable
0
1
Output Driver Impedence Control
0
Normal
1
Weak
QFC D.I.C
A
12
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