參數(shù)資料
型號: 21555-AA
英文描述: Controller Miscellaneous - Datasheet Reference
中文描述: 控制器雜項-數(shù)據(jù)表參考
文件頁數(shù): 27/30頁
文件大?。?/td> 485K
代理商: 21555-AA
Non-Transparent PPB
Datasheet
27
3.4.4
Serial ROM Timing Specifications
Table 13
shows the serial ROM timing specifications.
3.4.5
Parallel ROM Timing Specifications
Table 14
shows the parallel ROM timing specifications.
T
rrsus
s_req64_l asserted to s_rst_l deasserted
10*T
cyc
ns
a
T
rrval
s_rst_l to s_req64_l deasserted delay time
0 T
cyc
ns
a
T
rrsu
REQ64# to RST# deasserting setup time
T
cyc
ns
T
rrh
REQ64# from RST# deasserting hold time
0
50
ns
a. Applies to rising (deasserting) edge only.
Table 12. Reset Timing Specifications (Sheet 2 of 2)
Symbol
Parameter
Minimum
Maximum
Unit
Table 13. Serial ROM Timing Specifications
Symbol
Parameter
Minimum
Maximum
Unit
T
scval
pclk to pr_ad[0] serial ROM clock valid
14
ns
T
son
pr_ad
float to active delay
2
ns
T
soff
pr_ad active to float delay
28
ns
T
ssu
pr_ad[1] di to pr_ad[0] serial ROM clock setup time
400
ns
T
sh
pr_ad[1] to pr_ad[0] serial ROM clock hold time
20
ns
T
smcs
sr_cs minimum low time
400
ns
T
scyc
pr_ad[0] serial ROM clock
cycle time
1000
ns
Table 14. Parallel ROM Timing Specifications
Symbol
Parameter
Minimum
Maximum
Unit
T
pas
pr_ale_l setup to pr_clk rising
30
ns
T
pcc
pr_clk
cycle time
60
ns
T
pacs
pr_ale_l rising to pr_cs_l
falling
25
ns
T
pcsl
pr_cs_l
low
200
ns
T
pcrw
pr_cs_l falling to pr_rd_l or pr_wr_l falling
25
ns
T
prs
pr_ad setup time to pr_rd_l rising
180
ns
T
prh
pr_ad hold time from pr_rd_l rising
0
ns
T
prv
pr_clk rising to pr_ad valid
0
15
ns
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