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參數(shù)資料
| 型號(hào)： | 21555-AA |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 23/30頁(yè) |
| 文件大?。?/td> | 485K |
| 代理商： | 21555-AA |
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Non-Transparent PPB
Datasheet
23
3.3
DC Specifications
Table 7
defines the DC parameters met by all 21555 signals under the conditions of the functional
operating range.
Note:
In
Table 7
, currents into the chip (chip sinking) are denoted as positive (+) current. Currents from
the chip (chip sourcing) are denoted as negative (
–
) current.
3.4
AC Timing Specifications
The next sections specify the AC characteristics met by all 21555 signals under the conditions of
the functional operating range:
Clock timing.
PCI signal timing.
Reset timing.
Serial ROM timing.
Parallel ROM timing.
JTAG timing.
3.4.1
Clock Timing Specifications
The AC specifications consist of input requirements and output responses. The input requirements
consist of setup and hold times, pulse widths, and high and low times. The output responses are
delays from clock to signal. The AC specifications are defined separately for each clock domain
within the 21555.
Table 7. DC Parameters
Symbol
Parameter
Condition
Minimum
Maximum
Unit
V
cc
Supply voltage
—
3.0
3.6
V
V
il
Low-level input voltage
a
a. Guarantees meeting the specification for the 5-V signaling environment.
b. For 3.3-V signaling environment.
c.
For 5-V signaling environment.
d. Input leakage currents include high-Z output leakage for all bidirectional buffers with tristate outputs.
—
–
0.5
0.3 V
cc
V
V
ih
High-level input voltage
a
—
0.5 V
cc
V
IO
+ 0.5 V
V
V
ol
Low-level output voltage
b
I
out
= 1500 μA
—
0.1 V
cc
V
V
ol5V
Low-level output voltage
c
I
out
= 6 mA
—
0.55
V
V
oh
High-level output voltage
b
I
out
=
–
500 μA
0.9 V
cc
—
V
V
oh5V
High-level output voltage
c
I
out
=
–
2 mA
2.4
—
V
I
il
Low-level input leakage current
a,d
0 <V
in
<V
cc
—
±10
μA
C
in
Input pin capacitance
—
—
10.0
pF
C
IDSEL
p_idsel pin capacitance
—
—
8.0
pF
C
clk
p_clk, s_clk pin capacitance
—
5.0
12.0
pF
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