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| 型號(hào)： | 21555-AA |
| 英文描述： | Controller Miscellaneous - Datasheet Reference |
| 中文描述： | 控制器雜項(xiàng)-數(shù)據(jù)表參考 |
| 文件頁(yè)數(shù)： | 26/30頁(yè) |
| 文件大小： | 485K |
| 代理商： | 21555-AA |
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Non-Transparent PPB
26
Datasheet
3.4.3
Reset Timing Specifications
Table 12
shows the reset timing specifications for p_rst_l and s_rst_l.
Table 10. 33 MHz PCI Signal Timing Specifications
Symbol
Parameter
Minimum
Maximum
Unit
T
val
CLK to signal valid delay
—
bused signals
a,b,c
a. See
Figure 5
.
b. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.
c.
Point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. Bused signals are p_ad, p_cbe_l, p_par, p_par64,
p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par,
s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel.
2
11
ns
T
val(ptp)
CLK to signal valid delay
—
point-to-point
a,b,c
2
12
ns
T
on
Float to active delay
a,b
2
—
ns
T
off
Active to float delay
a,b
—
28
ns
T
su
Input setup time to CLK
—
bused signals
a,b,c
7
—
ns
T
su(ptp)
Input setup time to CLK
—
point-to-point
a,b,c
10, 12
—
ns
T
h
Input signal hold time from CLK
a,b
0
—
ns
Table 11. 66 MHz PCI Signal Timing Specifications
Symbol
Parameter
Minimum
Maximum
Unit
T
val
CLK to signal valid delay
—
bused signals
a,b,c
a. See
Figure 5
.
b. All primary interface signals are synchronized to p_clk. All secondary interface signals are synchronized to s_clk.
c.
Point-to-point signals are p_req_l, s_req_l[8:0], p_gnt_l, and s_gnt_l[8:0]. Bused signals are p_ad, p_cbe_l, p_par, p_par64,
p_perr_l, p_serr_l, p_frame_l, p_irdy_l, p_trdy_l, p_devsel_l, p_stop_l, p_idsel, p_req64_l, p_ack64_l, s_ad, s_cbe_l, s_par,
s_par64, s_perr_l, s_serr_l, s_frame_l, s_irdy_l, s_trdy_l, s_devsel_l, s_stop_l, s_req64_l, s_ack64_l, and s_idsel.
2
6
ns
T
val(ptp)
CLK to signal valid delay
—
point-to-point
a,b,c
2
6
ns
T
on
Float to active delay
a,b
2
—
ns
T
off
Active to float delay
a,b
—
14
ns
T
su
Input setup time to CLK
—
bused signals
a,b
3
—
ns
T
su(ptp)
Input setup time to CLK
—
point-to-point
a,b
5
—
ns
T
h
Input signal hold time from CLK
a,b
0
—
ns
Table 12. Reset Timing Specifications (Sheet 1 of 2)
Symbol
Parameter
Minimum
Maximum
Unit
T
rst
p_rst_l
active time after power stable
1
—
μs
T
rst-clk
p_rst_l active time after p_clk stable
100
—
μs
T
rst-off
p_rst_l active-to-output float delay
—
40
ns
T
srst
s_rst_l active after p_rst_l assertion
—
40
ns
T
srst-on
s_rst_l active time after s_clk stable
100
—
μs
T
dsrst
s_rst_l deassertion after p_rst_l deassertion
0
25
Cycles
–
p_rst_l slew rate
a
50
—
mV/ns
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