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參數(shù)資料
| 型號： | 21050 |
| 英文描述： | 21050 - 21050 PCI-to-PCI Bridge Hardware Implementation Application Note |
| 中文描述： | 21050 - 21050 PCI至PCI橋的硬件實(shí)現(xiàn)應(yīng)用筆記 |
| 文件頁數(shù)： | 6/15頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 21050 |
21050 PCI-to-PCI Bridge Hardware Implementation
6
Application Note
Clocks
One primary interface clock input (p_clk), one secondary interface clock input (s_clk), and
seven secondary interface clock outputs (s_clk_o<6:0>).
Diagnostic pins
One test input (goz_l) that tri-states all outputs, and one test output(nand_out) that is the output
of the diagnostic nand tree.
2.0
General Layout Guidelines
When using the 21050, consult the general layout guidelines provided in the
PCI Local Bus
Specification
Revision 2.0. Clock routing has some special requirements. Guidelines and
requirements for clock routing are discussed in the Clocking section of this document. Guidelines
for routing of secondary IDSEL signals are given in the Secondary IDSEL Mapping section. The
following sections discuss pullups and expansion card routing.
2.1
Pullups
Pullups are required on the following shared PCI control signals: FRAME#, IRDY#, TRDY#,
STOP#, DEVSEL#, PERR#, SERR#, and LOCK#. These signals must have pullups on both the
primary and secondary PCI buses. Even if optional shared signals such as LOCK# are not used,
they must be pulled up for proper 21050 operation. See the PCI Local Bus Specification for resistor
value guidelines.
If the 21050 is implemented on a motherboard, you must place both primary and secondary bus
pullups on the motherboard. If the 21050 is implemented on an option card with the primary bus
interfacing to the card edge, place primary bus pullups on the motherboard and place secondary bus
pullups on the option card.
Point-to-point and shared 32-bit signals do not require pullups. This includes the secondary arbiter
request/grant pairs and data synchronization signals. (If s_dispst_l is not used, however, tie it either
high or low through a resistor.)
2.2
Expansion Card Routing
Follow the guidelines and requirements for routing on expansion cards that are provided in the
PCI
Local Bus Specification
. The most important requirements are highlighted in this section.
PCI signals coming from the motherboard on the expansion card must be limited to only one load.
This includes the primary CLK. These are the signals on the primary interface of the 21050. These
signals also have trace length limitations, which are 1.5 inches for PCI signals and 2.5 inches for
the primary CLK.
PCI signals on the secondary side of the 21050, however, do not need to adhere to these restrictive
loading and trace length requirements. The secondary PCI bus can support the full 10 loads
(including the 21050) and essentially can be treated like a motherboard PCI bus.
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