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參數(shù)資料
| 型號(hào)： | 21050 |
| 英文描述： | 21050 - 21050 PCI-to-PCI Bridge Hardware Implementation Application Note |
| 中文描述： | 21050 - 21050 PCI至PCI橋的硬件實(shí)現(xiàn)應(yīng)用筆記 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 92K |
| 代理商： | 21050 |
21050 PCI-to-PCI Bridge Hardware Implementation
Application Note
5
1.0
Introduction
This document presents guidelines for hardware implementation of the 21050 in a system. This
application note is limited to hardware implementation of 21050 only and does not cover any
devices that might be behind the 21050, or initialization code needed to configure the 21050.
This application note includes implementation notes on layout, clocking, secondary bus IDSEL
mapping, using data synchronization pins, interrupt routing, and secondary bus arbitration.
Implementation on both a motherboard and an option card are covered. For most situations,
hardware implementation issues are the same. An exception is the clocking discussion, which
specifies separate guidelines for motherboard and option card implementations. In addition,
guidelines for interrupt routing on option cards are provided in the interrupt discussion.
The following related documents may be useful.
21050 PCI-PCI Bridge Data Sheet
21050 PCI-PCI Bridge Configuration Application Note
21050 PCI Evaluation Board User’s Guide
Published by the PCI Special Interest Group:
PCI Local Bus Specification
, Revision 2.0
PCI-PCI Bridge Architecture Specification
, Revision 1.0
1.1
Functional Overview
The 21050 PCI-PCI Bridge provides a connection between two independent PCI buses. The PCI
buses operate concurrently, except when reads or non posted writes are crossing the bridge. The
two PCI buses are referred to as the primary PCI bus, which is the PCI bus closest to the CPU, and
the secondary PCI bus, which is the PCI bus farther from the CPU.
The 21050 has two common applications. System designers can use the 21050 on a motherboard to
add more devices or add-in card slots than a single PCI bus can support. Add-in card designers can
use the 21050 to enable multiple device option cards. (PCI add-in cards are restricted to a single
connection to the signals in the PCI connector.) Designers can also use the 21050 to isolate bus
traffic on one PCI bus segment from other PCI bus segments.
The 21050 PCI-PCI Bridge has the following interfaces:
Primary and secondary PCI bus interfaces
Control and data to two PCI buses, including LOCK#, PERR#, and SERR#. To implement
these interfaces, follow the guidelines in the
PCI Local Bus Specification
, Revision 2.0. The
21050 primary interface implements Revision 2.0 compliant 5-Volt drivers.
Secondary bus arbiter
Six request/grant pairs for secondary bus master control, plus one pin, s_cfn_l, to enable the
arbiter.
Data synchronization pins
One control input (s_dispst_l) that marks posted write data and conditionally disables write
posting, and one control output (s_bufne_l) that indicates when marked data has been
delivered.
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