參數(shù)資料
型號： 16F872
廠商： Microchip Technology Inc.
英文描述： CAT 5E CROSSOVER PATCH CORD CABLE GREEN 10 FT
中文描述： 28引腳，8位閃存微控制器的CMOS
文件頁數(shù)： 27/160頁
文件大小： 2600K
代理商： 16F872
1999 Microchip Technology Inc.
Preliminary
DS30221A-page 27
PIC16F872
3.3
PORTC and the TRISC Register
PORTC is an 8-bit wide, bi-directional port. The corre-
sponding data direction register is TRISC.
Setting a
TRISC bit (=1) will make the corresponding PORTC pin
an input (i.e., put the corresponding output driver in a
hi-impedance mode). Clearing a TRISC bit (=0) will
make the corresponding PORTC pin an output (i.e., put
the contents of the output latch on the selected pin).
PORTC is multiplexed with several peripheral functions
(Table 3-5). PORTC pins have Schmitt Trigger input
buffers.
When the I
2
C module is enabled, the PORTC (3:4) pins
can be configured with normal I
2
C levels or with
SMBUS levels by using the CKE bit (SSPSTAT<6>).
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTC pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (
BSF, BCF, XORWF
) with TRISC as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
FIGURE 3-5:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<0:2>
RC<5:7>
FIGURE 3-6:
PORTC BLOCK DIAGRAM
(PERIPHERAL OUTPUT
OVERRIDE) RC<3:4>
Port/Peripheral Select
(2)
Data Bus
WR
Port
WR
TRIS
RD
Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Q
D
Q
CK
Q
D
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
V
DD
V
SS
Peripheral
OE
(3)
Peripheral Input
Note 1:
I/O pins have diode protection to V
DD
and V
SS
.
2:
Port/Peripheral select signal selects between port
data and peripheral output.
3:
Peripheral OE (output enable) is only activated if
peripheral select is active.
I/O
pin
(1)
Port/Peripheral Select
(2)
Data Bus
WR
Port
WR
TRIS
RD
Port
Data Latch
TRIS Latch
RD TRIS
Schmitt
Trigger
Q
D
Q
CK
Q
D
EN
Peripheral Data Out
0
1
Q
D
Q
CK
P
N
V
DD
Vss
Peripheral
OE
(3)
SSPl Input
I/O
pin
(1)
Note 1:
I/O pins have diode protection to V
DD
and V
SS
.
2:
Port/Peripheral select signal selects between port
data and peripheral output.
3:
Peripheral OE (output enable) is only activated if
peripheral select is active.
0
1
CKE
SSPSTAT<6>
Schmitt
Trigger
with
SMBus
levels
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