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| 型號： | 0W344-005-XTP |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 14/43頁 |
| 文件大小： | 0K |
| 描述： | DSP BELASIGNA 200 AUDIO 52-NQFN |
| 產品變化通告： | BelaSigna 200 QFN Obsolescence 09/Dec/2009 |
| 標準包裝： | 1,000 |
| 系列： | BelaSigna® 200 |
| 類型： | 音頻處理器 |
| 應用： | 便攜式設備 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 52-TFQFN 裸露焊盤 |
| 供應商設備封裝： | 52-NQFP（8x8） |
| 包裝： | 帶卷 (TR) |
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BelaSigna 200
The IOP places and retrieves FIFO data in memories shared with the RCore. Each FIFO (input and output) has two memory interfaces.
The first corresponds with the normal FIFO. Here the address of the most recent input block changes as new blocks arrive. The second
corresponds with the Smart FIFO. In this scheme the address of the most recent input block is fixed. The smart FIFO interface is
especially useful for time-domain filters.
In the case where the WOLA and the IOP no longer work together as a result of a low battery condition, an IOP end-of-battery-life auto-
mute feature is available.
7.3 General-Purpose Timer
The general-purpose timer is a 12-bit countdown timer with a 3-bit prescaler that interrupts the RCore when it reaches zero. It can
operate in two modes, single-shot or continuous. In single-shot mode the timer counts down only once and then generates an interrupt.
It will then have to be restarted from the RCore. In continuous mode the timer restarts with full timeout setting every time it hits zero and
interrupts are generated continuously. This unit is often useful in scheduling tasks that are not part of the sample-based signal
processing scheme, such as checking a battery voltage, or reading the value of a volume control.
7.4 Watchdog Timer
The watchdog timer is a configurable hardware timer that operates from the system clock and is used to prevent unexpected or
unstable system states. It is always active and must be periodically acknowledged as a check that an application is still running. Once
the watchdog times out, it generates an interrupt. If left to time out a second consecutive time without acknowledgement, a system reset
will occur.
7.5 RAM and ROM
There are 20 Kwords of on-chip program and data RAM on BelaSigna 200. These are divided into three entities: a 12-Kword program
memory, and two 4-Kword data memories ("X" and "Y" as are common in a dual-Harvard architecture).
There are also three RAM banks that are shared between the RCore and WOLA coprocessor. These memory banks contain the input
and output FIFOs, gain tables for the WOLA coprocessor, temporary memory for WOLA calculations, WOLA coprocessor results, and
the WOLA coprocessor microcode.
There is a 128-word lookup table (LUT) ROM that contains log2(x), 2
x, 1/x and sqrt(x) values, and a 1-Kword ProgramROM that is used
during booting and configuration of the system.
Complete memory maps for BelaSigna 200 are shown in Figure 11.
Rev. 16 | Page 21 of 43 | www.onsemi.com
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