參數(shù)資料
型號： 0W344-005-XTP
廠商： ON Semiconductor
文件頁數(shù)： 10/43頁
文件大?。?/td> 0K
描述： DSP BELASIGNA 200 AUDIO 52-NQFN
產(chǎn)品變化通告： BelaSigna 200 QFN Obsolescence 09/Dec/2009
標(biāo)準(zhǔn)包裝： 1,000
系列： BelaSigna® 200
類型： 音頻處理器
應(yīng)用： 便攜式設(shè)備
安裝類型： 表面貼裝
封裝/外殼： 52-TFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝： 52-NQFP（8x8）
包裝： 帶卷 (TR)
BelaSigna 200
7.0 Instruction Set
Table 6: Instruction Set
Instruction
Description
Instruction
Description
ABS A [,Cond] [,DW]
Calculate absolute value of A on condition
DCMP
Compare PH | PL to A
ADD A, Reg [,C]
Add register to A
DEC A [,Cond] [,DW]
Decrement A on condition
ADD A, (Rij) [,C]
Add memory to A
DEC Reg [Cond]
Decrement register on condition
ADD A, DRAM [,B]
Add (DRAM) to A
DEC (Rij) [,Cond]
Decrement memory on condition
ADD A, (Rij)p [,C]
Add program memory to A
DSUB [Cond] [,P]
Subtract PH | PL from A,
update PH | PL on condition
ADD A, Rc [,C]
Add Rc register to A
EOR A, Reg
Exclusive-OR register with AH to AH
ADDI A, IMM [,C]
Add IMM to A
EOR A, (Rij)
Exclusive-OR memory with AH to AH
ADSI A, SIMM
Add signed SIMM to A
EOR A, DRAM [,B]
Exclusive-OR (DRAM) with AH to AH
AND A, Reg
AND register with AH to AH
EOR A, (Rij)p
Exclusive-OR program memory with
AH to AH
AND A, (Rij)
AND memory with AH to AH
EOR A, Rc
Exclusive-OR Rc register with AH to
AH
AND A, DRAM [,B]
AND (DRAM) with AH to AH
EORI A, IMM
Exclusive-OR IMM with AH to AH
AND A, (Rij)p
AND program memory with AH to AH
EOSI A, SIMM
Exclusive-OR unsigned SIMM with AH
to AH
AND A, Rc
AND Rc register with AH to AH
INC A [,Cond] [,DW]
Increment A on condition
ANDI A, IMM
AND IMM with AH to AH
INC Reg [,Cond]
Increment register on condition
ANSI A, SIMM
AND unsigned SIMM with AH to AH
INC (Rij) [,Cond]
Increment memory on condition
BRA PRAM [,Cond]
Branch to new address on condition
LD Rc, Rc
Load Rc register with Rc register
BREAK
Stop the DSP for debugging purposes
LD Reg, Reg
Load register with register
CALL PRAM [,Cond] [,B]
Push PC and branch to new address
on condition
LD Reg, (Rij)
Load register with memory
CLB A
Calculate the leading bits on A
LD (Rij), Reg
Load memory with register
CLR A [,DW]
Clear accumulator
LD A, DRAM [,B]
Load A with (DRAM)
CLR Reg
Clear register
LD DRAM, A [,B]
Load (DRAM) with A
CMP A, Reg [,C]
Compare register to A
LD Rc, (Rij)
Load Rc register with memory
CMP A, (Rij) [,C]
Compare memory to A
LD (Rij), Rc
Load memory with Rc register
CMP A, DRAM [,B]
Compare (DRAM) to A
LD Reg, (Rij)p
Load register with program memory
CMP A, (Rij)p [,C]
Compare program memory to A
LD (Rij)p, Reg
Load program memory with register
CMP A, Rc [,C]
Compare Rc register to A
LD Reg, (Reg)p
Load register with program memory via
register
CMPI A, IMM [,C]
Compare IMM to A
LD Reg, Rc
Load register with Rc register
CMSI A, SIMM
Compare signed SIMM to A
LD Rc, Reg
Load Rc register with register
CMPL A [,Cond] [,DW]
Calculate logical inverse of A on condition
LDI Reg, IMM
Load register with IMM
DADD [Cond] [,P]
Add PH | PL to A, update PH | PL
on condition
LDI Rc, IMM
Load Rc register with IMM
DBNZ0/1 PRAM
Branch to new address if LC0/1 <> 0
LDI (Rij), IMM
Load memory with IMM
Rev. 16 | Page 18 of 43 | www.onsemi.com
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