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CHAPTER 16 SERIAL INTERFACE CHANNEL 0 (
m
PD78064Y Subseries)
(c) Interrupt timing specification register (SINT)
SINT is set by the 1-bit or 8-bit memory manipulation instruction.
RESET input sets SINT to 00H.
The SINT format is shown below, where the bits used in the I
2
C bus mode are shaded.
R/W
WAT1
0
0
1
WAT0
0
1
0
Interrupt control by wait
Note 2
Interrupt service request is generated on rise of 8th SCK0 clock cycle (clock output is high impedance).
Setting prohibited
Used in I
2
C bus mode (8-clock wait)
Generates an interrupt service request on rise of 8th SCL clock cycle. (In case of master device, SCL pin
is driven low after output of 8 clock cycles, to enter the wait state. In case of slave device, SCL pin is
driven low after input of 8 clock cycles, to require the wait state.)
Used in I
2
C bus mode (9-clock wait)
Generates an interrupt service request on rise of 9th SCL clock cycle. (In case of master device, SCL pin
is driven low after output of 9 clock cycles, to enter the wait state. In case of slave device, SCL pin is
driven low after input of 9 clock cycles, to require the wait state.)
1
1
R/W
WREL
0
1
Wait release control
Indicates that the wait state has been released.
Releases the wait state. Automatically cleared to 0 after releasing the wait state. This bit is used to release the
wait state set by means of WAT0 and WAT1.
R/W
CLC
0
1
Clock level control
Used in I
2
C bus mode. In cases other than serial transfer, SCL pin output is driven low.
Used in I
2
C bus mode. In cases other than serial transfer, SCL pin output is set to high impedance. (Clock line is
held high.) Used by master device to generate the start condition and stop condition signals.
R/W
SVAM
0
1
SVA bits used as slave address
Bits 0 to 7
Bits 1 to 7
R/W
SIC
0
1
INTCSI0 interrupt source selection
Note 3
CSIIF0 is set to 1 after end of serial interface channel 0 transfer.
CSIIF0 is set to 1 after end of serial interface channel 0 transfer or when stop condition is detected.
R
CLD
0
1
SCL pin level
Note 4
Low level
High level
Notes 1.
Bit 6 (CLD) is read-only.
2.
When the I
2
C bus mode is used, be sure to set 1 and 0, or 1 and 1 in WAT0 and WAT1, respectively.
3.
When using the wake-up function in I
2
C mode, be sure to set SIC to 1.
4.
When CSIE0 = 0, CLD is 0.
Remark
SVA: Slave address register
6
5
4
3
2
1
0
7
Symbol
SINT
0
CLD
SIC
Address After Reset R/W
SVAM CLC WREL WAT1 WAT0
FF63H 00H R/W
Note 1