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CHAPTER 19 INTERRUPT FUNCTIONS
(2) Interrupt mask flag registers (MK0L, MK0H, MK1L)
The interrupt mask flags are used to enable/disable the corresponding maskable interrupt service and to set
standby clear enable/disable.
MK0L, MK0H, and MK1L are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H
are combined to form a 16-bit register, they are set with a 16-bit memory manipulation instruction.
RESET input sets these registers to FFH.
Figure 19-3. Interrupt Mask Flag Register (MK0L, MK0H, MK1L) Format
Address: FFE4H After Reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
MK0L
STMK0
SRMK0
SERMK0
PMK3
PMK2
PMK1
PMK0
WDTMK
Address: FFE5H After Reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
MK0H
TMMK51
TMMK50
TMMK01
TMMK00
WTIMK
IICMK0
Note 1
CSIMK31
Note 2
CSIMK30
Address: FFE6H After Reset: FFH R/W
Symbol
7
6
5
4
3
2
1
0
MK1L
1
1
1
1
1
KRMK
WTMK
ADMK0
XXMKX
Interrupt Servicing Control
0
Interrupt servicing enabled
1
Interrupt servicing disabled
Notes 1.
Incorporated only in the
μ
PD780024 and 780034 Subseries. Be sure to set 1 for the
μ
PD780024Y,
780034Y Subseries.
2.
Incorporated only in the
μ
PD780024Y, 780034Y Subseries. Be sure to set 1 for the
μ
PD780024,
780034 Subseries.
Cautions 1. If the watchdog timer is used in watchdog timer mode 1, the contents of the WDTMK flag
become undefined when read.
2. Because port 0 pins have an alternate function as external interrupt request input, when
the output level is changed by specifying the output mode of the port function, an interrupt
request flag is set. Therefore, 1 should be set in the interrupt mask flag before using the
output mode.
3. Always set MK1L bits 3 to 7 to 1.