![](http://datasheet.mmic.net.cn/380000/-PD784214Y_datasheet_16744924/-PD784214Y_27.png)
27
23-40
23-41
23-42
23-43
Macro Service Data Transfer Processing Flow (Counter Mode) ........................................................... 466
Counter Mode ........................................................................................................................................ 467
Counting Number of Edges ................................................................................................................... 467
Interrupt Request Generation and Acknowledgment (Unit: Clock = 1/f
CLK
)............................................ 470
24-1
24-2
24-3
24-4
24-5
24-6
24-7
24-8
24-9
24-10
24-11
24-12
24-13
24-14
24-15
24-16
24-17
24-18
24-19
Memory Expansion Mode Register (MM) Format .................................................................................. 479
External Bus Type Selection Register (EBTS) Format .......................................................................... 480
Programmable Wait Control Register (PWC1) Format .......................................................................... 480
m
PD784214 Memory Map ...................................................................................................................... 482
m
PD784215 Memory Map ...................................................................................................................... 484
m
PD784216 Memory Map ...................................................................................................................... 486
Instruction Fetch from External Memory in Multiplexed Bus Mode........................................................ 489
Read Timing for External Memory in Multiplexed Bus Mode ................................................................. 490
External Write Timing for External Memory in Multiplexed Bus Mode ................................................... 491
Read Modify Write Timing for External Memory in Multiplexed Bus Mode ............................................ 492
Instruction Fetch from External Memory in Separate Bus Mode ........................................................... 494
Read Timing for External Memory in Separate Bus Mode..................................................................... 495
Write Timing for External Memory in Separate Bus Mode ..................................................................... 496
Read Modify Write Timing for External Memory in Separate Bus Mode................................................ 497
Read/Write Timing by Address Wait Function........................................................................................ 498
Read Timing by Access Wait Function................................................................................................... 502
Write Timing by Access Wait Function ................................................................................................... 504
Timing by External Wait Signal .............................................................................................................. 506
Example of Local Bus Interface ............................................................................................................. 507
25-1
25-2
25-3
25-4
25-5
25-6
25-7
25-8
25-9
25-10
25-11
25-12
25-13
25-14
Stand-by Function State Transitions ...................................................................................................... 510
Stand-by Control Register (STBC) Format ............................................................................................ 512
Clock Status Register (PCS) Format ..................................................................................................... 514
Oscillation Stabilization Time Setting Register (OSTS) Format ............................................................. 516
Operation after HALT Mode Release ..................................................................................................... 521
Operation after STOP Mode Release .................................................................................................... 530
Releasing STOP Mode by NMI Input ..................................................................................................... 532
Example of Releasing STOP Mode by INTP4 and INTP5 Inputs .......................................................... 533
Operation after IDLE Mode release ....................................................................................................... 537
Example of Handling Address/Data Bus ................................................................................................ 541
Flow for Setting Subsystem Clock Operation ........................................................................................ 543
Setting Timing for Subsystem Clock Operation ..................................................................................... 544
Flow To Restore Main System Clock Operation .................................................................................... 545
Timing for Restoring Main System Clock Operation .............................................................................. 545
26-1
26-2
Oscillation of Main System Clock in Reset Period ................................................................................. 551
Accepting Reset Signal.......................................................................................................................... 552
LIST OF FIGURES (7/8)
Figure No.
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