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CHAPTER 13 WATCHDOG TIMER
13.4 Cautions
13.4.1 General cautions when using the watchdog timer
(1) The watchdog timer is one way to detect runaway operation, but all runaway operations cannot be detected.
Therefore, in a device that particularly demands reliability, the runaway operation must be detected early not only
by the on-chip watchdog timer but by an externally attached circuit; and when returning to the normal state or
while in the stable state, processing like stopping the operation must be possible.
(2) The watchdog timer cannot detect runaway operation in the following cases.
<1>
<2>
When the watchdog timer is cleared in a timer interrupt servicing program
When there are successive temporary stores of interrupt requests and macro services (see
23.9 Temporarily
storing interrupt requests and macro services
)
When runaway operation is caused by logical errors in the program (when each module in the program
operates normally, but the entire system does not operate properly), and when the watchdog timer is
periodically cleared
When the watchdog timer is periodically cleared by an instruction group that is executed during runaway
operation
When the STOP, HALT, or IDLE mode is the result of runaway operation
When the watchdog timer also runs wild when the CPU runs wild because of introduced noise
<3>
<4>
<5>
<6>
In cases <1>, <2>, and <3>, detection becomes possible by correcting the program.
In case <4>, the watchdog timer can be cleared only by the 4-byte special instruction. Similarly in <5>, if there
is no 4-byte special instruction, the STOP, HALT, or IDLE mode cannot be set. Since the result of the runaway
operation is to enter state <2>, three or more bytes of consecutive data must be a specific pattern (example, BT
PSWL.bit, $$). Therefore, the results of <4>, <5>, and the runaway operation are believed to very rarely enter
state <2>.