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Example of Serial Bus Configuration Using I
2
C Bus .........................................................
Block Diagram of Clock-Synchronous Serial Interface (In I
2
C Bus Mode) .......................
Clocked Serial Interface Mode Register (CSIM) Format ...................................................
I
2
C Bus Control Register (IICC) Format .............................................................................
Prescaler Mode Register for Serial Clock (SPRM) Format ...............................................
Slave Address Register (SVA) Format ...............................................................................
Pin Configuration..................................................................................................................
Serial Data Transfer Timing on I
2
C Bus .............................................................................
Start Condition......................................................................................................................
Address.................................................................................................................................
Transfer Direction Specification ..........................................................................................
Acknowledge Signal .............................................................................................................
Stop Condition ......................................................................................................................
Wait Signal ...........................................................................................................................
Example of Communication from Master to Slave
(with 9-clock wait selected for both master and slave. Slave: WUP = 0)........................
Example of Communication from Slave to Master
(When selecting the 9th clock wait both master and slave) ..............................................
467
468
470
471
473
474
475
477
477
478
479
480
481
482
487
19-16
490
20-1
20-2
20-3
20-4
Clock Output Function Configuration ..................................................................................
Clock Output Mode Register (CLOM) Format ....................................................................
Clock Output Operation Timing ...........................................................................................
One-Bit Output Port Operation ............................................................................................
495
497
498
499
21-1
21-2
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21-5
21-6
External Interrupt Mode Register 0 (INTM0) Format .........................................................
External Interrupt Mode Register 1 (INTM1) Format .........................................................
Sampling Clock Selection Register (SCS0) Format ...........................................................
Edge Detection for Pins P20, P25 and P26 .......................................................................
P21 Pin Edge Detection.......................................................................................................
Edge Detection for Pins P22 to P24 ...................................................................................
502
503
504
505
506
507
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22-5
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22-7
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22-12
Interrupt Control Registers (
××
ICn) .....................................................................................
Interrupt Mask Register (MK0, MK1L) Format....................................................................
In-Service Priority Register (ISPR) Format.........................................................................
Interrupt Mode Control Register (IMC) Format...................................................................
Watchdog Timer Mode Register (WDM) Format ................................................................
Program Status Word (PSWL) Format ...............................................................................
Context Switching Operation by Execution of a BRKCS Instruction.................................
Return from BRKCS Instruction Software Interrupt (RETCSB Instruction Operation) .....
Non-Maskable Interrupt Request Acknowledgment Operations ........................................
Interrupt Acknowledgment Processing Algorithm...............................................................
Context Switching Operation by Generation of an Interrupt Request ...............................
Return from Interrupt that Uses Context Switching by Means of RETCS Instruction ......
518
521
523
524
525
526
527
528
530
534
535
536
LIST OF FIGURES (9/11)
Figure No.
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