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CHAPTER 3 CPU ARCHITECTURE
Table 3-5 List of Special Function Registers (SFRs) (4/5)
Address
Special Function Register (SFR) Name
Symbol
R/W
Manipulable Bit Units
After Reset
1 Bit
8 Bits 16 Bits
0FF8DH
Serial receive buffer: UART2
RXB2
R
—
√
—
Undefined
Serial transmit shift register: UART2
TXS2
W
—
√
—
Serial shift register: IOE2
SIO2
R/W
—
√
—
0FF90H
Baud rate generator control register
BRGC
—
√
—
00H
0FF91H
Baud rate generator control register 2
BRGC2
—
√
—
0FFA0H
External interrupt mode register 0
INTM0
√
√
—
0FFA1H
External interrupt mode register 1
INTM1
√
√
—
0FFA4H
Sampling clock selection register
SCS0
—
√
—
0FFA8H
In-service priority register
ISPR
R
√
√
—
0FFAAH
Interrupt mode control register
IMC
R/W
√
√
—
80H
0FFACH
Interrupt mask register 0L
MK0L
MK0
√
√
√
FFFFH
0FFADH
Interrupt mask register 0H
MK0H
√
√
0FFAEH
Interrupt mask register 1L
MK1L
√
√
—
FFH
0FFC0H
Standby control register
STBC
—
√
Note 2
—
30H
0FFC2H
Watchdog timer mode register
WDM
—
√
Note 2
—
00H
0FFC4H
Memory extension mode register
MM
√
√
—
20H
0FFC5H
Hold mode register
HLDM
√
√
—
00H
0FFC6H
Clock output mode register
CLOM
√
√
—
0FFC7H
Programmable wait control register 1
PWC1
—
√
—
AAH
0FFC8H
Programmable wait control register 2
PWC2
—
—
√
AAAAH
0FFCCH
Refresh mode register
RFM
√
√
—
00H
0FFCDH
Refresh area specification register
RFA
√
√
—
0FFCEH
Oscillation stabilization time specification register
OSTS
—
√
—
0FFD0H to
External SFR area
0FFDFH
—
√
√
—
—
0FFE0H
Interrupt control register (INTP0)
PIC0
√
√
—
43H
0FFE1H
Interrupt control register (INTP1)
PIC1
√
√
—
0FFE2H
Interrupt control register (INTP2)
PIC2
√
√
—
0FFE3H
Interrupt control register (INTP3)
PIC3
√
√
—
Notes
1.
When the LOCATION 0 instruction is executed. When the LOCATION 0FH instruction is executed, “F0000H”
should be added to the value shown.
2.
The write operation is possible by using the dedicated instruction “MOV STBC, #byte” or “MOV WDM, #byte”
only. Instructions other than these cannot perform the write operation.