
CHAPTER 7 8-BIT PWM TIMERS
97
(2) Cascade (16-bit timer) mode
Operation as interval timer (with 16-bit resolution)
The two PWM timers can be used as a 16-bit timer/counter by setting bit 4 (TMC5n4) of the 8-bit timer mode
control register 5n (TMC5n) to “1”.
In this case, the 16-bit timer/counter operates as an interval timer that repeatedly generates an interrupt
request at intervals specified by the count value set in advance to the 8-bit compare register 5n (CR5n).
Remark
n = 0 or 1
[Setting]
(1) Set each register.
TCL5n : The low-order timer selects the count clock.
The setting of the high-order cascaded timer is not necessary.
CR5n
: Compare value (Each compare value can be set in a range of 00H to FFH.)
TMC5n : Selects the clear & start mode in which the timers are cleared and started on
coincidence between TM5n and CR5n.
Low-order timer
TMC5n = 0000
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0B
¥
: don’t care
High-order timer
TMC5n = 0001
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0B
¥
: don’t care
(2) The counting is started when TCE5n of the high-order timer is set to 1 followed by setting of TCE5n
of the low-order timer to 1.
(3) When the values of TM5n and CR5n of the cascaded timers cascade coincide, INTTM5n is
generated by the low-order timer (all the TM5n’s are cleared to 00H).
(4) After that, INTTM5n is repeatedly generated at the same interval.
Cautions 1. Before setting the 8-bit compare register 5n (CR5n), be sure to stop the timer
operation.
2. Even when the timers are cascaded, if the count value of the high-order timer
coincides with the value of CR5n, INTT5n of the high-order timer is generated,
unless masked. Be sure to mask and disable the interrupt of the high-order timer.
3. Set TCE5n of the high-order timer first, and then that of the low-order timer.
4. The counting can be restarted or stopped by setting 1 or 0 to TCE5n of only the low-
order timer.
Remark
n = 0 or 1