
486
CHAPTER 24 INSTRUCTION SET
Clock
Flag
Note 1
Note 2
Z AC CY
SET1
saddr.bit
2
8
12
(saddr.bit)
←
1
sfr.bit
3
–
16
sfr.bit
←
1
A.bit
2
8
–
A.bit
←
1
PSW.bit
2
–
12
PSW.bit
←
1
×
×
×
[HL].bit
2
12
16 + 2n + 2m
(HL).bit
←
1
CLR1
saddr.bit
2
8
12
(saddr.bit)
←
0
sfr.bit
3
–
16
sfr.bit
←
0
A.bit
2
8
–
A.bit
←
0
PSW.bit
2
–
12
PSW.bit
←
0
×
×
×
[HL].bit
2
12
16 + 2n + 2m
(HL).bit
←
0
SET1
CY
1
4
–
CY
←
1
1
CLR1
CY
1
4
–
CY
←
0
0
NOT1
CY
1
4
–
CY
←
CY
×
CALL
!addr16
3
14
–
(SP – 1)
←
(PC + 3)
H
, (SP – 2)
←
(PC + 3)
L
,
PC
←
addr16, SP
←
SP – 2
CALLF
!addr11
2
10
–
(SP – 1)
←
(PC + 2)
H
, (SP – 2)
←
(PC + 2)
L
,
PC
15 – 11
←
00001, PC
10 – 0
←
addr11,
SP
←
SP – 2
CALLT
[addr5]
1
12
–
(SP – 1)
←
(PC + 1)
H
, (SP – 2)
←
(PC + 1)
L
,
PC
H
←
(00000000, addr5 + 1),
PC
L
←
(00000000, addr5),
SP
←
SP – 2
BRK
1
12
–
(SP – 1)
←
PSW, (SP – 2)
←
(PC + 1)
H
,
(SP – 3)
←
(PC + 1)
L
, PC
H
←
(003FH),
PC
L
←
(003EH), SP
←
SP – 3, IE
←
0
RET
1
12
–
PC
H
←
(SP + 1), PC
L
←
(SP),
SP
←
SP + 2
RETI
1
12
–
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3,
NMIS
←
0
R
R
R
RETB
1
12
–
PC
H
←
(SP + 1), PC
L
←
(SP),
PSW
←
(SP + 2), SP
←
SP + 3
R
R
R
Notes 1.
When the internal high-speed RAM area is accessed or when an instruction that does not access data
is executed
2.
When an area other than the internal high-speed RAM area is accessed
Remarks 1.
One clock of an instruction is equal to one CPU clock (f
CPU
) selected by processor clock control
register (PCC).
2.
The number of clocks shown is when the program is stored in the internal ROM area.
3.
n indicates the number of wait states when the external memory extension area is read.
4.
m indicates the number of wait states when the external memory extension area is written.
Mnemonic
Operand
Byte
Operation
Bit
manipulation
Instruction
Group
Call/return