
366
CHAPTER 17 SERIAL INTERFACE CHANNEL 1
Figure 17-4. Format of Automatic Data Transmit/Receive Control Register
Notes 1.
Bits 3 and 4 (TRF and ERR) are read-only bits.
2.
The completion of automatic transmission/reception should be determined with TRF instead of
CSIIF1 (interrupt request flag).
Caution
Set STRB and BUSY1 of ADTC to 0, 0 when external clock input is selected by setting bit
1 (CSIM11) of the serial operation mode register 1 (CSIM1) to 0.
Remark
×
: Don’t care
6
5
4
3
2
1
0
7
Symbol
ADTC
RE
ARLD ERCE ERR
TRF
STRB
BUSY1BUSY0
BUSY1
0
1
1
Controls busy input
Does not use busy input
Enables busy input (high active)
Enables busy input (low active)
BUSY0
×
0
1
STRB
0
1
Controls strobe output
Disables strobe output
Enables strobe output
TRF
1
Status of automatic transmit/receive function
Note 2
Detects end of automatic transmission/reception
(set to 0 when automatic transmission/reception is
aborted, or when ARLD = 0)
Automatic transfer/reception is in progress (set to
1 when this bit is written to SIO1)
R/W
R/W
R
R
ERR
0
1
Error detection of automatic
transmit/receive
function
No error during automatic
transmission
/reception
(set to 0 when this bit is written to SIO1)
Error during automatic
transmission
/reception
R/W
ARLD
0
1
Selects operation mode of automatic
transmit/
receive
function
Single mode
Repeated mode
R/W
RE
0
1
Controls reception of automatic
transmit/receive
function
Disables reception
Enables reception
R/W
ERCE
Controls error check of automatic
transmit/receive
function
Disables error check during automatic
transmission
/
reception
Enables error check during automatic
transmission
/
reception (only when BUSY1 = 1)
0
FF69H 00H R/W
Note 1
Address On reset R/W
0
1