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CHAPTER 18 INTERRUPT FUNCTIONS AND TEST FUNCTIONS
0
6
5
4
3
2
1
0
7
PSW
IE
Z
RBS1
AC
RBS0
0
ISP
CY
02H
On reset
IE
0
1
Enables/disables accepting interrupt request
Disables
Enables
ISP
Priority of interrupt currently processed
Interrupt with higher priority is processed (interrupt
with lower priority is disabled)
Interrupt is not accepted, or interrupt with lower
priority is processed (all maskable interrupts are
enabled)
Used when normal instruction is executed
1
Symbol
(6) Program status word (PSW)
The program status word is a register that holds the instruction execution result and current status of interrupt
request. An IE flag that enables/disables the maskable interrupts and an ISP flag that controls nesting
processing are mapped to this register.
This register can be read or written in 8-bit units. In addition, it can also be manipulated by using a bit
manipulation instruction or dedicated instructions (EI and DI). When a vectored interrupt request is accepted,
and when the BRK instruction is executed, PSW is automatically saved to the stack. At this time, the IE flag
is reset to 0. If a maskable interrupt request has been accepted the content of the priority flag of that interrupt
is transferred to ISP flag. The contents of PSW can also be saved to the stack by the PUSH PSW instruction,
and restored from the stack by RETI, RETB or POP PSW instruction.
PSW is set to 02H when the RESET signal is input.
Figure 18-8. Configuration of Program Status Word
18.4 Interrupt Processing Operation
18.4.1 Non-maskable interrupt request acceptance operation
The non-maskable interrupt request is unconditionally accepted even when interrupts are disabled. It is not subject
to interrupt priority control and takes precedence over all other interrupts.
When the non-maskable interrupt request is acknowledged, program status word (PSW) and program counter (PC)
are saved to the stack in that order, the IE flag and ISP flag are reset to 0, the contents of the vector table are loaded
to the PC, and then program execution branches.
If a new non-maskable interrupt request is generated while the non-maskable interrupt service program is executed,
the interrupt request is accepted when the current execution of the non-maskable interrupt service program has been
completed (after the RETI instruction has been executed) and one instruction in the main routine has been executed.
If two or more new non-maskable interrupt requests are generated while the non-maskable interrupt service program
is executed, only one non-maskable interrupt request is accepted after execution of the non-maskable interrupt service
program has been completed.
Figure 18-9 shows the flowchart from generation of the non-maskable interrupt to accepting it. Figure 18-10 shows
the timing of accepting the non-maskable interrupt, and Figure 18-11 shows the operation performed if the non-
maskable interrupt occurs in duplicate.