參數(shù)資料
型號: μPD75P3036
廠商: NEC Corp.
英文描述: 4 Bit Single Chip Microcontrollers(4 位單片微控制器)
中文描述: 4位單片微控制器(4位單片微控制器)
文件頁數(shù): 46/64頁
文件大?。?/td> 382K
代理商: ΜPD75P3036
46
m
PD75P3036
Data retention characteristics of data memory in STOP mode and at low supply voltage
(T
A
= –40 to +85 °C)
Parameter
Symbol
Conditions
MIN.
TYP.
MAX.
Unit
Release signal setup time
t
SREL
0
m
s
ms
Oscillation stabilization
t
WAIT
Released by RESET
2
15
/f
X
wait time
Note 1
Released by interrupt request
Note 2
ms
Notes 1.
The oscillation stabilization wait time is the time during which the CPU stops operating to prevent
unstable operation when oscillation is started.
Set by the basic interval timer mode register (BTM). (Refer to the table below.)
2.
BTM3
BTM2
BTM1
BTM0
Wait Time
f
X
= 4.19 MHz
f
X
= 6.0 MHz
0
0
0
2
20
/f
X
(approx. 250 ms)
2
20
/f
X
(approx. 175 ms)
0
1
1
2
17
/f
X
(approx. 31.3 ms)
2
17
/f
X
(approx. 21.8 ms)
1
0
1
2
15
/f
X
(approx. 7.81 ms)
2
15
/f
X
(approx. 5.46 ms)
1
1
1
2
13
/f
X
(approx. 1.95 ms)
2
13
/f
X
(approx. 1.37 ms)
Data retention timing (when STOP mode released by RESET)
Data retention timing (standby release signal: when STOP mode released by interrupt signal)
STOP mode
Data retention mode
Operation mode
Oscillation stabilization wait time
t
SREL
V
DDDR
t
WAIT
STOP instruction execution
V
DD
Standby release signal
(interrupt request)
STOP mode
Data retention mode
Internal reset operation
Operation mode
STOP instruction execution
Oscillation stabilization wait time
V
DD
RESET
V
DDDR
t
WAIT
t
SREL
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