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CHAPTER 3 CPU FUNCTIONS
3.4.10 Specific registers
Specific registers are registers that are protected from being written with illegal data due to erroneous program
execution, etc. The write access of these specific registers is executed in a specific sequence, and if abnormal
store operations occur, it is notified by the system status register (SYS). The V853 has two specific registers, the
clock control register (CKC) and power save control register (PSC). For details of the CKC register, refer to
6.3.3
,
and for details of the PSC register, refer to
6.5.2
.
The following shows the access sequence of the specific registers.
The specific register is programmed in the following special sequence:
<1> The interrupt disable is set (PSW NP bit is set to 1).
<2> Any 8-bit data is written in the command register (PRCMD).
<3> The setting data is written in the specific register (using the following instructions).
Store instruction (ST/SST instruction)
Bit manipulation instruction (SET1/CLR1/NOT1 instruction)
<4> The interrupt disable is released (PSW NP bit is set to 0).
<5> The NOP instruction (2 or 5 instructions) is inserted.
No special sequence is necessary for reading the specific register.
Cautions 1. If interrupts are accepted in the time between the PRCMD issue (<2>) and the specific register
writing (<3>) directly after, the specific register is not written and protection error (SYS
register PRERR bit is “1”) is generated in some cases. Therefore, set the PSW NP bit to 1
(<1>) and disable the INT/NMI acceptance.
The same applies when the bit manipulation instruction is used to set the specific register.
Insert the NOP instruction (<5>) as the dummy instruction so that the routine is executed
correctly after the STOP/IDLE mode is released. If the PSW ID bit value is not to be changed
by the execution of the instruction which returns the NP bit to 0 (<4>), insert two NOP
instructions. If it is to be changed, insert five.
The following are examples.
[Example] : Case of PSC register
LDSR rX,5
ST.B
r0,PRCMD [r0] ; Writing in PRCMD
ST.B
rD,PSC [r0]
LDSR rY,5
NOP
.
NOP
(next instruction)
.
; NP bit = 1
; Sets PSC register
; NP bit = 0
; Dummy instruction (2 or 5 instructions)
; Execution routine after STOP/IDLE mode has been released
rX: Value written in PSW
rY: Value written back to PSW
rD: Value set to PSC