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CHAPTER 14 FLASH MEMORY (μPD70F3003 AND 70F3003A)
14.5.3 Reset pin
When connecting the reset signals of the dedicated flash programmer to the RESET pin which is connected to
the reset signal generation circuit on-board, conflict of signals occurs. To avoid the conflict of signals, isolate the
connection to the reset signal generation circuit.
When reset signal is input from the user system during the flash memory programming mode, programming
operation will not be performed correctly. Therefore, do not input signals other than the reset signals from the
dedicated flash programmer.
14.5.4 NMI pin
The input signal to the NMI pin is ignored during the flash memory programming mode.
14.5.5 MODE pin
To switch to the flash memory programming mode, connect MODE pin to V
DD
, applies writing voltage (10 V) to
V
PP
pin, and release the reset.
14.5.6 Port pin
When the flash memory programming mode is set, all the port pins except the pins which communicate with the
dedicated flash programmer become output high-impedance status. The treatment of these port pins are not
necessary. If problems such as disabling output high-impedance status should occurs to the external devices
connected to the port, connect them to V
DD
or V
SS
through resistors.
14.5.7 WAIT pin
Connect WAIT pin to V
DD
directly.
14.5.8 Other signal pin
Connect X1, X2, CKSEL (μPD703003A, 70F3003A, 703005A), and AV
REF1
to AV
REF3
to the same status as that
in the normal operation mode.
14.5.9 Power supply
Supply the power supply (V
DD
, V
SS
, AV
DD
, AV
SS
, CV
DD
, CV
SS
) same as that in normal operation mode. Connect
V
DD
and GND of the dedicated flash programmer to V
DD
and V
SS
. Always connect V
DD
of the dedicated flash
programmer because it is provided with power supply monitoring function.
RESET
Dedicated flash programmer connection pin
Conflict of signals
Output pin
Reset signal generation circuit
V853
In the flash memory programming mode, the
signal the reset signal generation circuit outputs
conflicts with the signal the dedicated flash
programmer outputs. Therefore, isolate the
signals on the reset signal generation circuit side.