參數(shù)資料
型號(hào): μPD703002
廠商: NEC Corp.
英文描述: 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述: 16/32位單片機(jī)微控制器(16/32位單片微控制器)
文件頁(yè)數(shù): 56/72頁(yè)
文件大小: 528K
代理商: ΜPD703002
56
μ
PD703002
(5) Read timing (1/2)
Parameter
Symbol
Condition
MIN.
MAX.
Unit
CLKOUT
↑ →
Address delay time
<20>
t
DKA
3
20
ns
CLKOUT
↑ →
Address float time
<21>
t
FKA
3
15
ns
CLKOUT
↓ →
ASTB delay time
<22>
t
DKST
3
15
ns
CLKOUT
↑ →
DSTB delay time
<23>
t
DKD
3
15
ns
CLKOUT
↑ →
Status delay time
<24>
t
DKS
3
15
ns
Data input setup time (to CLKOUT
)
<25>
t
SIDK
5
ns
Data input hold time (from CLKOUT
)
<26>
t
HKID
5
ns
WAIT setup time (to CLKOUT
)
<27>
t
SWTK
5
ns
WAIT hold time (from CLKOUT
)
<28>
t
HKWT
5
ns
Address hold time (from CLKOUT
)
<29>
t
HKA
0
ns
Address setup time (to ASTB
)
<30>
t
SAST
0.5T–10
ns
Address hold time (from ASTB
)
<31>
t
HSTA
0.5T–10
ns
DSTB
↓ →
Address float delay time
<32>
t
FDA
0
ns
Data input setup time (to address)
<33>
t
SAID
(2+n)T–20
ns
Data input setup time (to DSTB
)
<34>
t
SDID
(1+n)T–20
ns
ASTB
↓ →
DSTB
delay time
<35>
t
DSTD
0.5T–10
ns
Data input hold time (from DSTB
)
<36>
t
HDID
0
ns
DSTB
↑ →
Address output delay time <37>
t
DDA
(1+i)T
ns
DSTB
↑ →
ASTB
delay time
<38>
t
DDSTH
0.5T–10
ns
DSTB
↑ →
ASTB
delay time
<39>
t
DDSTL
(1.5+i)T–10
ns
Status setup time (to ASTB
)
<40>
t
SSST
0.5T–10
ns
Status hold time (from ASTB
)
<41>
t
HSTS
0.5T–10
ns
DSTB low-level width
<42>
t
WDL
(1+n)T–10
ns
ASTB high-level width
<43>
t
WSTH
T–10
ns
WAIT setup time (to address)
<44>
t
SAWT1
n
1
1.5T–20
ns
<45>
t
SAWT2
(1.5+n)T–20
ns
WAIT hold time (from address)
<46>
t
HAWT1
n
1
(0.5+n)T
ns
<47>
t
HAWT2
(1.5+n)T
ns
WAIT setup time (to ASTB
)
<48>
t
SSTWT1
n
1
T–15
ns
<49>
t
SSTWT2
(1+n)T–15
ns
WAIT hold time (from ASTB
)
<50>
t
HSTWT1
n
1
nT
ns
<51>
t
HSTWT2
(1+n)T
ns
Remarks 1.
T = t
CYK
n indicates the number of wait clocks inserted in a bus cycle. The sampling timing varies when
programmable wait states are inserted.
i indicates the number of idle states (0 or 1) inserted in the read cycle.
Satisfy at least one of the data input hold times t
HKID
(<26>) and t
HDID
(<36>).
2.
3.
4.
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