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參數(shù)資料
| 型號(hào)： | μPD703002 |
| 廠商： | NEC Corp. |
| 英文描述： | 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器) |
| 中文描述： | 16/32位單片機(jī)微控制器（16/32位單片微控制器） |
| 文件頁(yè)數(shù)： | 40/72頁(yè) |
| 文件大?。?/td> | 528K |
| 代理商： | ΜPD703002 |
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40
μ
PD703002
Table 11-2. Symbols Shown in “Operation Code” Column
Symbol
Meaning
R
1-bit-wise data of code specifing reg1 or regID
r
1-bit-wise data of code specifing reg2
d
1-bit-wise data of displacement
i
1-bit-wise data of immediate
cccc
4-bit data indicating condition code
bbb
3-bit data specifing bit number
Table 11-3. Symbols Shown in "Operation" Column
Symbol
Meaning
←
Assignment
GR [ ]
General register
SR [ ]
System register
zero-extend (n)
Zero-extends "n" to word length
sign-extend (n)
Sign-extends "n" to word length
load-memory (a, b)
Reads data of size "b" from address "a"
store-memory (a, b, c)
Writes data "b" of size "c" to address "a"
load-memomy-bit (a, b)
Reads bit "b" of address "a"
store-memory-bit (a, b, c)
Writes "c" to bit "b" of address "a"
saturated (n)
Performs saturated processing of n (n is 2's complement)
"n" indicates result of operation.
If "n"
≥
7FFFFFFFH, 7FFFFFFFH
If "n"
≤
80000000H, 80000000H
result
Reflects result on flag
Byte
Byte (8 bits)
Halfword
Halfword (16 bits)
Word
Word (32 bits)
+
Add
–
Subtract
||
Bit concatenation
×
Multiply
÷
Divide
AND
Logical product
OR
Logical sum
XOR
Exclusive logical sum
NOT
Logical negation
logically shift left by
Logical left shift
logically shift right by
Logical right shift
arithmetically shift right by
Arithmetic right shift
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