參數(shù)資料
型號(hào)： μPD703002
廠商： NEC Corp.
英文描述： 16/32 Bit Single Chip Microcontrollers(16/32 位單片微控制器)
中文描述： 16/32位單片機(jī)微控制器（16/32位單片微控制器）
文件頁數(shù)： 18/72頁
文件大?。?/td> 528K
代理商： ΜPD703002
μ
PD703002
18
Table 5-1. Interrupts
Interrupt/Exception Causes
Default Exception
Handler
Restore
Type
Class
Name
Control
Register
Generation Cause
Generating
Unit
Priority
Code
Address
PC
Reset
Interrupt
RESET
—
Reset input
—
—
0000H
00000000H
Undefined
Non-maskable
Interrupt
NMI
—
NMI input
—
—
0010H
00000010H next PC
Software exception
Exception
TRAP0n
Note
—
TRAP instruction
—
—
004n
Note
H
00000040H next PC
Exception
TRAP1n
Note
—
TRAP instruction
—
—
005n
Note
H
00000050H next PC
Exception trap
Exception
ILGOP
—
Illegal instruction code
—
—
0060H
00000060H next PC
Maskable
Interrupt
INTOV1
OVIC1
Timer 1 overflow
RPU
0
0080H
00000080H next PC
Interrupt
INTP10/INTCC10
P1IC0
Match of INTP10 & CC10
Pin/RPU
1
0090H
00000090H next PC
Interrupt
INTP11/INTCC11
P1IC1
Match of INTP11 & CC11
Pin/RPU
2
00A0H
000000A0H next PC
Interrupt
INTP12/INTCC12
P1IC2
Match of INTP12 & CC12
Pin/RPU
3
00B0H
000000B0H next PC
Interrupt
INTP13/INTCC13
P1IC3
Match of INTP13 & CC13
Pin/RPU
4
00C0H
000000C0H next PC
Interrupt
INTCM4
CMIC4
Match of CM4
RPU
5
00D0H
000000D0H next PC
Interrupt
INTCSI0
CSIC0
CSI0 transmit/receive
SIO
6
00E0H
000000E0H next PC
completion
Interrupt
INTSER0
SEIC0
UART0 receive error
SIO
7
00F0H
000000F0H next PC
Interrupt
INTSR0
SRIC0
UART0 receive completion
SIO
8
0100H
00000100H next PC
Interrupt
INTST0
STIC0
UART0 transmit completion
SIO
9
0110H
00000110H next PC
Interrupt
INTP00
P0IC0
INTP00 pin
Pin
10
0120H
00000120H next PC
Interrupt
INTP01
P0IC1
INTP01 pin
Pin
11
0130H
00000130H next PC
Interrupt
INTP02
P0IC2
INTP02 pin
Pin
12
0140H
00000140H next PC
Interrupt
INTP03
P0IC3
INTP03 pin
Pin
13
0150H
00000150H next PC
Interrupt
INTCSI1
CSIC1
CSI1
transmit/receive completion
SIO
14
0160H
00000160H next PC
Interrupt
INTCSI2
CSIC2
CSI2
transmit/receive completion
SIO
15
0170H
00000170H next PC
Note
The "n" in the "Software exception" rows is a value from 0 to FH.
Remarks 1.
Default priority:
Priority used when two or more maskable interrupt requests having the
same priority are simultaneously generated. 0 indicates the highest
priority.
Restore PC: PC value saved to EIPC or FEPC when interrupt/exception processing is started.
However, the restore PC value saved if an interrupt is accepted while the DIVH
(division) instruction is being executed is the PC value of the current instruction
(DIVH).
The execution address of an illegal instruction when an illegal instruction code exception
occurs can be calculated as (restore PC–4).
2.
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