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參數(shù)資料
| 型號(hào)： | μPD4811650 |
| 廠商： | NEC Corp. |
| 英文描述： | 16M Synchronous Graphics Memory (SGRAM)(16M同步圖形存儲(chǔ)器) |
| 中文描述： | 1,600同步圖形存儲(chǔ)器（SGRAM）（1,600同步圖形存儲(chǔ)器） |
| 文件頁數(shù)： | 7/96頁 |
| 文件大?。?/td> | 1517K |
| 代理商： | ΜPD4811650 |
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7
μ
PD4811650 for Rev. E
Preliminary Data Sheet
1. Input/Output Pin Function
Pin name
Input/Output
Function
CLK
Input
CLK is the master clock input. Other inputs signals are referenced to the CLK rising edge.
CKE
Input
CKE determine validity of the next CLK (clock). If CKE is high, the next CLK rising edge is
valid; otherwise it is invalid. If the CLK rising edge is invalid, the internal clock is not asserted
and the
μ
PD4811650 suspends operation.
When the
μ
PD4811650 is not in burst mode and CKE is negated, the device enters power
down mode. During power down mode, CKE must remain low.
In Self refresh mode, low level on this pin is also used as part of the input command to
specify Self refresh.
/CS
Input
/CS low starts the command input cycle. When /CS is high, commands are ignored but
operations continue.
/RAS, /CAS,
/WE
Input
/RAS, /CAS and /WE have the same symbols on conventional DRAM but different functions.
For details, refer to the command table.
DSF
Input
DSF is part of the inputs of graphics command of the
μ
PD4811650.
If DSF is inactive (Low level),
μ
PD4811650 operates as same as SDRAM.
Row Address is determined by A0 - A9 at the CLK (clock) rising edge in the activate
A0 - A9
Input
command cycle.
Column Address is determined by A0 - A7 at the CLK rising edge in the read or write
command cycle.
A9 defines the precharge mode. When A9 is high in the precharge command cycle, both
banks are precharged; when A9 is low, only the bank selected by A10 is precharged.
When A9 is high in read or write command cycle, the precharge starts automatically after the
burst access.
A10
A10 is the bank address signal (BA). In command cycle, A10 low selects bank A and A10
high selects bank B.
DQM0 - DQM3 Input
DQM controls I/O buffers. DQM0 corresponds to the lowest byte (DQ0 to DQ7), DQM1
corresponds to DQ8 to DQ15, DQM2 corresponds to DQ16 to DQ23. DQM3 corresponds to
DQ24 to DQ31.
In read mode, DQM controls the output buffers like a conventional /OE pin.
DQM high and DQM low turn the output buffers off and on, respectively.
The DQM latency for the read is two clocks.
In write mode, DQM controls the word mask. Input data is written to the memory cell if DQM
is low but not if DQM is high.
The DQM latency for the write is zero.
DQ0 - DQ31
Input/Output
DQ pins have the same function as I/O pins on a conventional DRAM.
These are normally 32-bit data bus and are used for inputting and outputting data.
Function as the mask data input pins in the special register set command.
Write operations can be performed after Active command with WPB (old mask data).
Functions as the column selection data input pin in the block write cycle.
V
CC
, V
SS
,
V
CC
Q,V
SS
Q
(Power supply)
V
CC
and V
SS
are power supply pins for internal circuits. V
CC
Q and V
SS
Q are power supply pins
for the output buffers.
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