參數(shù)資料
型號： ZPSD601(V)E1
英文描述： Field Programmable Microcontroller Peripherals with Embedded Micro--Cell(可編程邏輯，零功耗，4K位SRAM,26個可編程I/O,通用PLD有63個輸入)
中文描述： 現(xiàn)場可編程微控制器外圍設備和嵌入式微-細胞（可編程邏輯，零功耗，4K的位的SRAM，26余個可編程輸入/輸出，通用PLD的有63個輸入）
文件頁數(shù)： 44/98頁
文件大?。?/td> 484K
代理商： ZPSD601(V)E1
ZPSD6XX(V) Family
12-44
I/O Ports
(cont.)
Port Operating Modes
(cont.)
Address In Mode
For microcontrollers that have more than 16 address lines, the higher addresses can be
connected to Port A, B, or C. The address input can be latched in the Input Micro
Cell by
ALE. Any input that is included in the DPLD equations for the PSD EPROM and SRAM is
considered as address input.
Data Port Mode
Port A and B can be used as data bus ports for a microcontroller with a non-multiplexed
address/data bus. The Data Port is connected to the data bus of the microcontroller. The
general I/O functions are disabled in Port A or B if the port is configured as Data Port.
Peripheral I/O Mode
Only Port A supports the Peripheral I/O mode where all of Port A serves as a tri-state
capable bi-directional data buffer of the microcontroller’s data bus. Peripheral mode is
enabled by setting Bit 7 of the VM Register to a “1”. Figure 22 shows that when Peripheral
mode is enabled and either PSEL0 and PSEL1 from the DPLD is active, Port A acts as a
bi-directional buffer for the microcontroller D[7:0] data bus. The buffer is tri-stated when
PSEL 0 or 1 is not active. The Peripheral I/O mode can be used to interface with external
peripherals.
Open Drain/Slew Rate Mode
Port A (pins PA7-4), Port B (pins PB7-4) or Port C (except PC2) can be configured as an
open drain instead of CMOS outputs. The Open Drain configuration is useful for sinking
large currents to operate relays or LEDs, for example. The Open Drain mode is enabled by
writing a “1” to the corresponding bit in the Drive Register.
Port A (PA3–0), Port B (PB3–0) and Port D can be configured as ECSPLD outputs that
have a high slew rate. The high slew rate is enabled by writing a “1” to the corresponding
bit in the Drive Register.
RD
PSEL0
PSEL1
VM REGISTER BIT 7
WR
PA0-PA7
D0-D7
DATA BUS
Figure 22. Port A Peripheral Mode
相關PDF資料
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