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參數(shù)資料
| 型號(hào)： | Z9974CA |
| 英文描述： | DIODE TVS 16V 500W BI-DIR |
| 中文描述： | 共14名分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 52PIN |塑料 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | Z9974CA |
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07090 Rev. *A
06/18/2001
Page 6 of 9
Z9974
AC Parameters
Characteristic
Output Duty Cycle
Symbol
Tpw
Min
Typ
Max
Tcycle/2
+ 800
1.5
10
250
100
Units
ps
Conditions
Measured @ VDD/2
Tcycle/2
- 800
0.15
Tcycle/2
+ 500
-
7
-
-
Rise Time / Fall Time
Output Impedance
Output to Output Skew
Propagation Delay,
TCLK(0:1) to FBIN
Cycle to Cycle Jitter
Output Disable Time
T
r,
T
f
Z
o
T
s
T
pd
ns
ps
ps
Measured between 0.8V and 2.0V
-
All output equally loaded
Measured for 50MHz at VDD/2
-250
tj
-
2
+100
-
-
ps
ns
Measured for 50 MHz at VDD/2
After MR# goes low
tPLZ,
tPHZ
tPZL
Fout
10
Output Enable Time
Maximum Output
Frequency
2
-
-
-
10
125
63
42
ns
MHz
After MR# goes High
Q (
÷
2)
Q (
÷
4)
Q (
÷
6)
VDD* = 3.3V + 5%, TA = -40
°
C to +85
°
C
Note: Parameters are guaranteed by design and characterization. Not 100% tested in production. All parameters
specified with loaded outputs. Z9974 outputs can drive series or parallel terminator 50
(or 50
to VDD/2).
Test Circuit Diagram
NOTE: All buffer outputs are tied to a common 3.3 Volt VDD (VDD*) for testing purposes
PROBE
VDD*
Impedance
7
Output under Test
43
50
1K
1K
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