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參數(shù)資料
| 型號(hào)： | Z9974CA |
| 英文描述： | DIODE TVS 16V 500W BI-DIR |
| 中文描述： | 共14名分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 52PIN |塑料 |
| 文件頁(yè)數(shù)： | 5/9頁(yè) |
| 文件大?。?/td> | 62K |
| 代理商： | Z9974CA |
3.3V, 125MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07090 Rev. *A
06/18/2001
Page 5 of 9
Z9974
Maximum Ratings
Input Voltage Relative to VSS:
Input Voltage Relative to VDD:
Storage Temperature:
Operating Temperature:
Maximum Power Supply:
VSS-0.3V
VDD+0.3V
-65
°
C to + 150
°
C
-40
°
C to +85
°
C
5.5V
This device contains circuitry to protect the inputs
against damage due to high static voltages or electric
field; however, precautions should be taken to avoid
application of any voltage higher than the maximum
rated voltages to this circuit. For proper operation, Vin
and Vout should be constrained to the range:
VSS<(Vin or Vout)<VDD
Unused inputs must always be tied to an appropriate
logic voltage level (either VSS or VDD).
DC Parameters
Characteristic
Input Low Voltage
Input High Voltage
Input Low Current
Input High Current
Output Low Voltage
Output High Voltage
Quiescent Supply Current
Input Pin Capacitance
Symbol
VIL
VIH
IIL
IIH
VOL
VOH
Idd
Cin
Min
VSS
2.0
Typ
-
-
Max
0.8
VDD
-100
100
0.5
Units
Vdc
Vdc
μA
μA
Conditions
Applicable to all input signals.
V
V
IOL = 20 mA
IOH = - 20mA
2.4
-
-
-
-
20
8
mA
pF
Per input
VDD* =3.3V + 5%, TA = -40
°
C to +85
°
C
PLL AC Parameters
Characteristic
Maximum PLL Lock Time
Symbol
tLOCK
Min
Typ
Max
10
Units
mS
Conditions
Stable power supply & valid clocks
presented on TCLK(0:1) pins.
FselFB(0:1) = /4 to /12
VCO Lock Range
TCLK(0:1) input rise / fall
time
Input Reference frequency
Input Reference duty cycle
fVCO
Tinr, Tinf
200
500
3
MHz
nS
fREF
fREFpw
Note 1
25
Note 1
75
MHz
%
VDD* = 3.3V + 5%, TA = -40
°
C to +85
°
C
Note 1:
Input Reference Frequency is limited by the divider selection and the VCO lock range.
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