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參數(shù)資料
| 型號(hào)： | Z9953AA |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):20A; Peak Non Repetitive Surge Current, Itsm:300A; Gate Trigger Current Max, Igt:30uA |
| 中文描述： | 八分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 32腳|塑料 |
| 文件頁(yè)數(shù)： | 2/6頁(yè) |
| 文件大?。?/td> | 43K |
| 代理商： | Z9953AA |
3.3V, 180MHz, Multi-Output Zero Delay Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07086 Rev. *A
06/18/2001
Page 2 of 6
Z9953
Pin Description
PIN
8
9
12, 14, 16,
18, 20, 22,
24, 26
28
NAME
PWR
I/O
I
I
O
Description
PECL_CLK
PECL_CLK#
Q(7:0)
PECL Input Clock.
PECL Input Clock.
Clock Output.
VDDC
FB_OUT
VDDC
O
Feedback Clock Output. Connect to FB_IN for normal
operation. A bypass delay capacitor at this output will
control Input Reference / Output phase relationships.
Feedback Clock Input. Connect to FB_OUT for accessing
the PLL.
Master Reset/Output Enable Input. When asserted high,
resets all of the internal flip-flops and also disables all of the
outputs. When pulled low, releases the internal flip-flops
from reset and enables all of the outputs.
PLL Select Input. When asserted high, VCO output is
selected. And when set low, PECL_CLK is the input to the
output dividers.
PLL Enable Input. When high, PLL is enabled and when
low, PLL is bypassed.
VCO Divider Select Input. When set high, VCO output is
divided by 2. When set low, the divider is bypassed.
3.3V Power Supply for Output Clock Buffers.
2
FB_IN
I
10
MR/OE#
I
30
PLL_EN
I
31
BYPASS#
I
32
VCO_SEL
I
11, 15, 19,
23, 27
1
7, 13, 17, 21,
25, 29
3, 4, 5, 6
PD = Internal Pull-Down, PU = Internal Pull-Up.
VDDC
VDD
VSS
3.3V Power Supply for PLL
Common Ground
NC
No Connection
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