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參數(shù)資料
| 型號(hào)： | Z9305DZ |
| 英文描述： | FIVE DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|8PIN|PLASTIC |
| 中文描述： | 五分布式輸出時(shí)鐘驅(qū)動(dòng)器|專(zhuān)科| 8引腳|塑料 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 134K |
| 代理商： | Z9305DZ |
Z9305/Z9309
Document #: 38-07196 Rev. **
Page 4 of 7
Maximum Ratings
Voltage Relative to V
SS
.................................................–
0.3V
Voltage Relative to V
DD
..................................................0.3V
Storage Temperature .................................
–
65
°
C to + 150
°
C
Operating Temperature.................................
–
40
°
C to +85
°
C
Maximum Power Supply ....................................................7V
Reference Input Voltage ........................................
–
0.5 to 7V
DC Electrical Characteristics (Z9305/Z9309)
(V
DD
= 3.0
–
3.6V, T
A
=
–
40
°
C to 85
°
C)
This device contains circuitry to protect input against damage
from high static voltages or electric fields. Precautions should
be taken, however, to avoid applications to this circuit of any
voltage higher than the maximum rated voltages. For proper
operation, V
IN
and V
OUT
should be constrained to the range:
V
SS
< (V
IN
or V
OUT
) < V
DD
.
Unused inputs must always be tied to an appropriate logic
voltage level (either V
SS
or V
DD
).
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Units
V
IL
V
IH
Input LOW Voltage4
–
–
0.8
Vdc
Input HIGH Voltage4
–
2.0
–
Vdc
I
IL
Input LOW Current
V
IN
= 0V
50.0
μA
I
IH
V
OL
Input HIGH Current
V
IN
= V
DD
I
OL
= 8 mA
±
100
μA
Output LOW Voltage5
0.4
V
V
OH
Output HIGH Voltage5
I
OH
=
–
8mA
2.4
V
Ioz
3-state Leakage Current
S1 = S2 = GND
–
–
10
μA
Idd
Power-Down Supply Current
Ref = 0 MHz
–
–
50
μA
Idd
Dynamic Supply Current
Unload outputs, 66.66 MHz, select
inputs at V
DD
or GND.
–
–
40
mA
Switching Characteristics (Z9305/Z9309)
(V
DD
= 3.0
–
3.6V, T
A
=
–
40
°
C to 85
°
C)
Parameter
Description
Test Conditions
Min.
Typ.
Max.
Units
Fin
Frequency
Duty Cycle (T
2
/T
1
)
[6]
Rise Time
[6]
30 pF load
10
150
MHz
–
Measured @ 1.4V
45
50
55
%
t
3
Measured between 0.8V and 2.0V
15 pF Load
–
1.5
nSec
t
4
Fall Time
[6]
Measured between 0.8V and 2.0V
15 pF Load
1.5
nSec
t
5
Output-to-Output Skew
[6]
All output equally loaded
–
–
250
pSec
t
6
Delay, REF Rising Edge to
CLKOUT Rising Edge
[6]
Measured at V
DD
/2
–
0
+ 350
pSec
t
7
Device-to-Device Skew
[6]
Measured at V
DD
/2 on FBK pins of
devices
-
0
700
pSec
tj
Cycle-to-Cycle Jitter
[6]
Measured at 66.67 MHz, loaded
outputs, input Trise/Fall < 1 nS
–
–
200
pSec
tLOCK
Maximum PLL Lock Time
[6]
Stable power supply, valid clocks
presented on REF pin.
1.0
ms
Notes:
4.
5.
6.
REF and FBK inputs have a threshold voltage of V
/2.
Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
Parameter is guaranteed by design and characterization. Not 100% tested in production. All parameters specified with loaded outputs.
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