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參數資料
| 型號： | Z9305DZ |
| 英文描述： | FIVE DISTRIBUTED-OUTPUT CLOCK DRIVER|SOP|8PIN|PLASTIC |
| 中文描述： | 五分布式輸出時鐘驅動器|?？苵 8引腳|塑料 |
| 文件頁數： | 3/7頁 |
| 文件大小： | 134K |
| 代理商： | Z9305DZ |
Z9305/Z9309
Document #: 38-07196 Rev. **
Page 3 of 7
Zero Delay and Skew Control
All outputs should be uniformly loaded to achieve sero delay
between input and output. Since the CLKOUT pin is the
internal feedback to the PLL, its relative loading can adjust the
input-output delay. This is shown in the above graph.
For applications requiring zero I/O delay, all outputs including
CLKOUT must be equally loaded. Even if CLKOUT is not used,
it must have a load capacity equal to that of other outputs. If
input-to-output delay adjustments are required, use the above
graph to calculate loading differences between the CLKOUT
pin and other outputs. For zero output-output skew, be sure to
load all outputs equally.
Z9309 Select Input Functionality
S2
S1
CLKA1-A4
CLKB1-B4
CLK-OUT
[3]
Output Source
PLL Shut-down
0
0
3-state
3-state
Driven
PLL
N
0
1
Driven
3-state
Driven
PLL
N
1
0
Driven
Driven
Driven
REF
Y
1
1
Driven
Driven
Driven
PLL
N
0
-5
-10
-15
-20
-25
-30
5
10
15
20
25
30
1500
1000
500
0
-500
-1000
-1500
R
Output Load Difference: CLKOUT Load - CLKA/CLKB Load (PF)
REF, Input T0 CLKA/CLKB Delay versus Loading Difference Between CLKOUT and CLKA/CLKB Pins
Note:
3.
This output is driven and has an internal feedback for the PLL. The load on this output can be adjusted to change the skew between the reference and outputs.
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