參數(shù)資料
型號(hào)： Z9104CAB
英文描述： SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):8A; Peak Non Repetitive Surge Current, Itsm:100A; Gate Trigger Current Max, Igt:15uA
中文描述： 六分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 32腳|塑料
文件頁(yè)數(shù)： 6/8頁(yè)
文件大?。?/td> 69K
代理商： Z9104CAB
Variable Delay Motherboard Clock Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07083 Rev. *A
5/07/2001
Page 6 of 8
Z9104
APPROVED PRODUCT
VDDA
+
-
3.3V
.01uF
22uF
Z9104
Device
R
s
Fig. 3
Figure 3 shows the recommended power supply decoupling circuitry to obtain minimum device clock noise (jitter).
Designs shown implement this decoupling scheme in noisy VDD environments to protect the device’s internal analog
circuitry from digital noise born on the main 3.3 volt supply. A range of 2.2 to 15 ohms is recommended for R
s
. R
s
should
be adjusted to the minimum value required to produce acceptable performances from the device. The ultimate limitation
on the R
s
maximum value is the device’s minimum VDDA spec.
Frequency Applications Examples
Table 1. Z9104 Example Min/Max Frequency Table
Mode
FBS1
FBS0
REFIN Frequency
Min. (MHz)
50
REFIN Frequency
Max (MHz)
100
CLK(25:6), Output
Frequency (MHz)
Example:
1
0
0
1 x REFIN
REFIN = 66.7 MHz
CLK* = 66.7 MHz
REFIN = 66.7 MHz
CLK* = 83.3 MHz
REFIN = 66.7 MHz
CLK* = 100 MHz
REFIN = 33.3 MHz
CLK* = 33.3 MHz
REFIN = 33.3 MHz
CLK* = 66.7 MHz
REFIN = 33.3 MHz
CLK* = 83.3 MHz
REFIN = 33.3 MHz
CLK* = 100 MHz
REFIN = 33.3 MHz
CLK* = 50 MHz
1
0
1
40
80
1.25 x REFIN
1
1
0
33.3
66.7
1.5 x REFIN
1
1
1
25
50
1 x REFIN
0
0
0
25
50
2 x REFIN
0
0
1
20
40
2.5 x REFIN
0
1
0
16.7
33.3
3 X REFIN
0
1
1
16.7
33.3
1.5 X REFIN
32
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