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參數(shù)資料
| 型號(hào)： | Z9104CAB |
| 英文描述： | SCR Thyristor; SCR Type:Standard Gate; Peak Repetitive Off-State Voltage, Vdrm:800V; On-State RMS Current, IT(rms):8A; Peak Non Repetitive Surge Current, Itsm:100A; Gate Trigger Current Max, Igt:15uA |
| 中文描述： | 六分布式輸出時(shí)鐘驅(qū)動(dòng)器| TQFP封裝| 32腳|塑料 |
| 文件頁(yè)數(shù)： | 2/8頁(yè) |
| 文件大?。?/td> | 69K |
| 代理商： | Z9104CAB |
Variable Delay Motherboard Clock Buffer
Cypress Semiconductor Corporation
525 Los Coches St.
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571
http://www.cypress.com
Document#: 38-07083 Rev. *A
5/07/2001
Page 2 of 8
Z9104
APPROVED PRODUCT
Pin Description
PIN No.
2
3
Pin Name
REFIN
PLLEN
PWR
VDDI
VDD
I/O
I
I
Description
External reference clock input pin.
This pin routes the REFIN clock to the normal PLL output circuitry when at a
logic low level. It is intended to be used for static testing of the parts internal
logic.
Feedback selection pins. These input pins control the internal routing of the
feedback output clock that produce the multiplier values listed in the “Feedback
Scale Select Code” table on page 1.
Combined with the FBS pins, this pin determines the output clocks frequency
with respect to the REFIN pin. See table on page 1 for functionality.
Output Enable for all CLK output clocks. When at a logic low level, all outputs
are driven to a Tri State.
Stop Clock for all CLK output clocks. When at a logic low level CLK (1:6) are
driven to a logic low level synchronously with their next occurring high to low
transition. This signal does NOT effect the FBOUT clock.
Clock source that is used in the device’s external feedback loop. This pin is
connected to the device’s FBIN pin either directly or through an external delay
circuit.
2.5 Volt output clock copy of CLK2:6
These output clocks are the synthesized product of the REFIN clock and the
selections programmed on the FB0, FB1 and MODE pins.
Ground pins for the device.
3.3 Volt Power supply pins for clock buffer circuit
3.3 volt power supply pins for the FBOUT clock output buffers.
Synchronous output enable control pin for CLK25.
Synchronous output enable control pin for CLK2 and CLK3 pins.
Synchronous output enable control pin for CLK4 pins.
Synchronous output enable control pin for CLK5 pins.
Synchronous output enable control pin for CLK6 pins.
2.5 volt power supply pin for the CLK25 clock output buffers.
Analog power. See recommended circuitry later in this datasheet.
Ground supply for pin 15 (FBOUT) buffer.
Ground power connection for analog circuitry.
Ground power connection for input clock circuitry.
3.3V power connection for input clock circuitry.
4, 5
FBS(0:1)
VDD
I
31
MODE
VDD
I
6
OEALL
VDD
I
7
STOPCLK
VDD
I
15
FBOUT
VDDF
O
27
CLK25
CLK(2:6)
VDD25
VDD
O
O
25, 23, 21,
19, 17
20, 24, 28
18, 22
14
30
29
12
11
10
26
32
16
9
8
1
NOTES:
1.
Pins with “PU” or “PD” listed in the Type column indicate that these pins have internal pull-up or pull down resistors. These resistors
ensure that the device will sense a logic 1 (high) or logic 0 (low) condition respectively when the device is powered up and no
electrical connection is made to these pins.
2.
All synchronous output enables, when driven to a logic low level, will cause their associated output clocks to transition to a logic low
level and remain there. Likewise, they will cause their associated output clocks to begin running when driven to a logic high level.
This enabling and disabling action will produce no runt (short or long) clock output cycles.
VSS
VDD
VDDF
SC25
SC2:3
SC4
SC5
SC6
VDD25
VDDA
VSSF
VSSA
VSSI
VDDI
---
---
---
P
P
P
I
I
I
I
I
P
P
P
P
P
P
VDD
VDD
VDD
VDD
VDD
---
---
---
---
---
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