參數(shù)資料
型號： Z86E8316VSC
英文描述： MICROCONTROLLER|8-BIT|Z8 CPU|CMOS|LDCC|28PIN|PLASTIC
中文描述： 單片機(jī)| 8位| Z8的CPU |的CMOS | LDCC | 28腳|塑料
文件頁數(shù)： 38/52頁
文件大?。?/td> 483K
代理商： Z86E8316VSC
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-38
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION
(Continued)
The D/A conversion for DAC1 is driven by writing 8-bit data
to the DAC1 data register (Bank C, Register 06H). The
D/A conversion for DAC2 is controlled by the DAC2 data
register (Bank C, Register 07H). Each DAC data register
is initialized to midrange 80H on power-up.
There are two DAC control registers: DACR1 (Bank C,
Register 04H) for DAC1, and DACR2 (Bank C, Register
05H) for DAC2. Control register bits 0 and 1 set the DAC
gain. When DAC data is 80H, the DAC output is constant
for any gain setting (Figure 29 and Figure 31).
Figure 29. D/A 1 Control Register
Figure 30. D/A 1 Data Register
D7
D6
D5
D4
D3
D2
D1
D0
DAC1 Gain
0 0 1 X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DACR1 Bank C, Register 4
DAC1 Enable
0 Disable
1 Enable
Reserved (Must be 0)
D7
D6
D5
D4
D3
D2
D1
D0
DAC1 Bank C, Register 6
0 = Low Level
1 = High Level
Figure 31. D/A 2 Control Register
Figure 32. D/A 2 Data Register
D7
D6
D5
D4 D3
D2
D1
D0
DAC2 Gain
0 0 1 X
0 1 1/2 X
1 0 1 Not Used
1 1 1/4 X
DACR2 Bank C, Register 5
DAC2 Enable
(Must be 0 for C83)
0 Disable
1 Enable
Reserved (Must be 0)
D7
D6
D5
D4
D3
D2
D1
D0
DAC2 Bank C, Register 7
0 = Low Level
1 = High Level
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