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參數(shù)資料
| 型號(hào)： | Z86E8316VSC |
| 英文描述： | MICROCONTROLLER|8-BIT|Z8 CPU|CMOS|LDCC|28PIN|PLASTIC |
| 中文描述： | 單片機(jī)| 8位| Z8的CPU |的CMOS | LDCC | 28腳|塑料 |
| 文件頁數(shù)： | 30/52頁 |
| 文件大小： | 483K |
| 代理商： | Z86E8316VSC |
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Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-30
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION
(Continued)
Register File.
The Register File consists of three I/O port
registers, 237 general-purpose registers, 15 control and
status registers, and four system configuration registers in
the Expanded Register Group (Figure 16). The instruc-
tions can access registers directly or indirectly through an
8-bit address field. This allows a short 4-bit register ad-
dress using the Register Pointer (Figure 18). In the 4-bit
mode, the Register File is divided into 16 working register
groups, each occupying 16 continuous locations. The
Register Pointer (Figure 17) addresses the starting loca-
tion of the active working-register group.
Note:
Register Bank E0-EF is only accessed either as
working registers or through indirect addressing modes.
CAUTION: D4 of Control Register P01M (R251) must
be 0.
R254.
The C83/C84/E83 has one extra general-purpose
register located at FEH (R254).
Stack.
The C83/C84/E83 has an 8-bit Stack Pointer
(R255) used for the internal stack that resides within the
236 general-purpose registers. Register R254 cannot be
used for stack.
General-Purpose Registers (GPR).
These registers are
undefined after the device is powered up. The registers
keep their last value after any reset, as long as the reset
occurs in the V
CC
voltage-specified operating range. It will
not keep its last state from a V
LV
reset if the V
CC
drops be-
low 1.8V. This includes Register R254.
Note:
Register Bank E0-EF is only accessed either as
working register or through indirect addressing modes.
RAM Protect.
The upper portion of the RAM’s address
spaces %80F to %EF (excluding the control registers) are
protected from writing. The user activates this feature from
the internal ROM code to turn off/on the RAM Protect by
loading either a 0 or 1 into the Interrupt Mask (IMR) regis-
ter, bit D6. A 1 in D6 enables RAM Protect.
Figure 17. Register Pointer Register
D7
D6
D5
D4
D3
D2
D1
D0
Expanded Register Group
Working Register Group
RP
R253
Note: Default Setting After Reset = 00000000
Figure 18. Register Pointer
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
r7
r6
r5
r4
R253
(Register Pointer)
I/O Ports*
Specified Working
Register Group
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
r3
r2
r1
r0
Register Group 1
Register Group 0*
R15 to R0
R15 to R4*
R3 to R0*
R15 to R0
FF
F0
0F
00
1F
10
2F
20
3F
30
4F
40
5F
50
6F
60
7F
70
* Expanded Register File Bank (0) is selected
in this figure by handling bits D3 to D0 as "0"
in Register R253 (RP).
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