參數(shù)資料
型號(hào)： Z86E8316VSC
英文描述： MICROCONTROLLER|8-BIT|Z8 CPU|CMOS|LDCC|28PIN|PLASTIC
中文描述： 單片機(jī)| 8位| Z8的CPU |的CMOS | LDCC | 28腳|塑料
文件頁(yè)數(shù)： 28/52頁(yè)
文件大?。?/td> 483K
代理商： Z86E8316VSC
Z86C83/C84/E83
CMOS Z8
MCU
Zilog
8-28
P R E L I M I N A R Y
DS97DZ80700
FUNCTIONAL DESCRIPTION
RESET.
(Input, Active Low). This pin initializes the MCU.
Reset is accomplished either through Power-On Reset
(POR), Watch-Dog Timer (WDT) Reset, or external reset.
During POR, and WDT Reset, the internally generated re-
set is driving the reset pin Low for the POR time.
Any de-
vices driving the reset line must be open-drain to
avoid damage from a possible conflict during reset
conditions.
Pull-up is provided internally.
After the POR time, /RESET is a Schmitt-triggered input.
After the reset is detected, an internal RST signal is
latched and held for an internal register count of 18 exter-
nal clocks, or for the duration of the external reset, which-
ever is longer. Program execution begins at location 000C
(hex), 5-10 TpC cycles after the RST is released. For POR,
the reset output time is T
POR
.
Program Memory.
C83/C84/E83/E84 can address up to
4 KB of internal Program Memory (Figure 15). The first 12
bytes of program memory are reserved for the interrupt
vectors. These locations contain six 16-bit vectors that cor-
respond to the six available interrupts. Bytes 13 to 4095
consist of on-chip, mask-programmed ROM.
ROM Protect.
The 4 KB of Program Memory is mask pro-
grammable. A ROM protect feature will prevent dumping
of the ROM contents from an external program outside the
ROM.
Expanded Register File.
The register file has been ex-
panded to allow for additional system control registers and
for mapping of additional peripheral devices and input/out-
put ports into the register address area. The Z8 register
address space R0 through R15 is implemented as 16
groups of 16 registers per group (Figure 16). These regis-
ter banks are known as the Expanded Register File (ERF).
Bits 3-0 of the Register Pointer (RP) select the active ERF
bank. Bits 7-4 of register RP select the working register
group (Figure 16). Four system configuration registers re-
side in the ERF address space in Bank F and eight regis-
ters reside in Bank C. The rest of the ERF addressing
space is not physically implemented, and is open for future
expansion.
Note:
When using Zilog's Cross Assembler version 2.1 or
earlier, use the LD RP, #0X instruction rather than the SRP
#0X instruction to access the ERF.
Figure 15. Program Memory Map
12
11
10
9
8
7
6
5
4
3
2
1
0
On-Chip
ROM
Location of
First Byte of
Instruction
Executed
After RESET
Interrupt
Vector
(Lower Byte)
Interrupt
Vector
(Upper Byte)
IRQ5
IRQ4
IRQ4
IRQ3
IRQ3
IRQ2
IRQ2
IRQ1
IRQ1
IRQ0
IRQ0
IRQ5
2048/4096
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