參數(shù)資料
型號(hào)： XRT91L32IQ-F
廠商： EXAR CORP
元件分類(lèi)： 數(shù)字傳輸電路
英文描述： STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述： TRANSCEIVER, PQFP100
封裝： 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
文件頁(yè)數(shù)： 7/37頁(yè)
文件大?。?/td> 417K
代理商： XRT91L32IQ-F
xr
REV. 1.0.2
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
5
CDRREFSEL
LVTTL
I
98
Clock and Data Recover Unit Reference Frequency Select
Selects the Clock and Data Recovery Unit reference frequency
based on the table below.
"Low" = CDR uses CMU’s reference clock
"High" = CDR reference clock from CDRAUXREFCLK
N
OTE
:
CDRAUXREFCLK requires accuracy of 77.76 MHz
+/- 500ppm.
LOOPTIME
LVTTL
I
5
Loop Timing Mode
When the loop timing mode is activated the external reference
clock to the input of the Retimer is replaced with the high-speed
recovered receive clock from the CDR.
"Low" = Disabled
"High" = Loop timing Activated
CDRDIS
LVTTL
I
23
Clock and Data Recovery Unit Disable
Active "High." Disables internal Clock and Data Recovery unit.
Received serial data bypasses the integrated CDR block.
RXINP/N is then sampled on the rising edge of externally
recovered differential clock XRXCLKIP/N coming from the opti-
cal module.
"Low" = Internal CDR unit is Enabled
"High" = Internal CDR unit is Disabled and Bypassed
VDD /
(PIO_CTRL )
LVTTL
I
81
Transmit Parallel Clock Directional Control
Transmit Parallel Clock Output Operation
If this pin is asserted "High", TXPCLK_IO is a parallel bus clock
output. Data on the TXDI[7:0] must be synchronously applied
prior to the sampling by the PISO at the rising edge of
TXPCLK_IO clock output driven by the XRT91L30.
RLOOPS
LVTTL
I
1
Serial Remote Loopback
The serial remote loopback mode interconnects the receive
serial data input to the transmit serial data output. If serial
remote loopback is enabled, the 8-bit parallel transmit data
input is ignored while the 8-bit parallel receive data output is
maintained.
"Low" = Disabled
"High" = Serial Remote Loopback Mode Enabled
N
OTE
:
DLOOP and RLOOPS can be enabled simultaneously
to achieve a dual loopback diagnostic feature in normal
operation.
N
AME
L
EVEL
T
YPE
P
IN
D
ESCRIPTION
CDRREFSEL
STS12/
STS3
CDRAUXREFCLK
F
REQUENCY
D
ATA
R
ATE
0
CDR uses CMU’s reference clock
(see CMUFREQSEL pin)
1
0
77.76 MHz
STS-3/STM-1
155.52 Mbps
1
1
77.76 MHz
STS-12/STM-4
622.08 Mbps
相關(guān)PDF資料
PDF描述
XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80_0507 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L80IB 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
XRT91L81IB 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT91L32IQTR 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT91L32IQTR-F 功能描述:LIN 收發(fā)器 PHY Transceiver RoHS:否 制造商:NXP Semiconductors 工作電源電壓: 電源電流: 最大工作溫度: 封裝 / 箱體:SO-8
XRT91L33 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:STS-12/STS-3 MULTIRATE CLOCK AND DATA RECOVERY UNIT
XRT91L33AIG-F 制造商:Exar Corporation 功能描述:CDR 155.52Mbps/622.08Mbps SONET/SDH 20-Pin TSSOP
XRT91L33ES 功能描述:界面開(kāi)發(fā)工具 Eval System for XRT91L33 Series RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
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