參數(shù)資料
型號(hào): XRT91L32IQ-F
廠商: EXAR CORP
元件分類: 數(shù)字傳輸電路
英文描述: STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
中文描述: TRANSCEIVER, PQFP100
封裝: 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, QFP-100
文件頁(yè)數(shù): 17/37頁(yè)
文件大?。?/td> 417K
代理商: XRT91L32IQ-F
xr
REV. 1.0.2
XRT91L32
STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
15
T
ABLE
6: C
LOCK
AND
D
ATA
R
ECOVERY
U
NIT
P
ERFORMANCE
Jitter specification is defined using a 12kHz to 1.3/5MHz LP-HP single-pole filter.
1
These reference clock jitter limits are required for the outputs to meet SONET system level jitter requirements (<10 mUI
rms
).
2
Required to meet SONET output frequency stability requirements.
2.3.1
Optionally, the internal CDR unit can be disabled and bypassed in lieu of an externally recovered clock.
Asserting the CDRDIS "High" disables the internal Clock and Data Recovery unit and the received serial data
bypasses the integrated CDR block. RXINP/N is then sampled on the rising edge of the externally recovered
differential clock XRXCLKIP/N coming from the optical module or an external clock recovery unit. Figure 5
shows the possible internal paths of the recovered clock and data.
Internal Clock and Data Recovery Bypass
N
AME
P
ARAMETER
M
IN
T
YP
M
AX
U
NITS
REF
DUTY
Reference clock duty cycle
40
60
%
REF
JIT
Reference clock jitter (rms) with 19.44 MHz reference
1
5
ps
REF
JIT
Reference clock jitter (rms) with 77.76 MHz reference
1
13
ps
REF
TOL
Reference clock frequency tolerance
2
-20
+20
ppm
TOL
JIT
Input jitter tolerance with 1 MHz < f < 20 MHz PRBS pattern
0.3
0.4
UI
OCLK
FREQ
Frequency output
620
624
MHz
OCLK
DUTY
Clock output duty cycle
40
60
%
F
IGURE
5. I
NTERNAL
C
LOCK
AND
D
ATA
R
ECOVERY
B
YPASS
RXIP
RXIN
M
CDR
M
CDRDIS
Clk
Data
XRXCLKIP
XRXCLKIN
DATA
CLOCK
SIPO
Div by 8 CLOCK
Parallel DATA
8
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