參數(shù)資料
型號(hào)： XRT86VL3X_07
廠商： Exar Corporation
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 7/153頁(yè)
文件大?。?/td> 1316K
代理商： XRT86VL3X_07
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)當(dāng)前第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)
XRT86VL3X
IV
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
LIST OF FIGURES
Figure 1.: XRT86VL3x N-Channel DS1 (T1/E1/J1) Framer/LIU Combo ........................................................................... 1
Figure 2.: LIU Transmit Connection Diagram Using Internal Termination ......................................................................... 4
Figure 3.: LIU Receive Connection Diagram Using Internal Termination ......................................................................... 4
Figure 4.: Simplified Block Diagram of the Transmit Interface for 1:1 and 1+1 Redundancy ............................................ 5
Figure 5.: Simplified Block Diagram of the Receive Interface for 1:1 and 1+1 Redundancy ............................................. 6
Figure 6.: Simplified Block Diagram of a Non-Intrusive Monitoring Application ................................................................. 7
Figure 7.: Transmit T1/E1 Serial PCM Interface ................................................................................................................ 8
Figure 8.: Receive T1/E1 Serial PCM Interface ................................................................................................................. 8
Figure 9.: T1 Fractional Interface ....................................................................................................................................... 9
Figure 10.: T1/E1 Time Slot Substitution and Control ..................................................................................................... 10
Figure 11.: Robbed Bit Signaling / CAS Signaling ........................................................................................................... 11
Figure 12.: ESF / CAS External Signaling Bus ................................................................................................................ 11
Figure 13.: SF / SLC-96 or 4-code Signaling in ESF / CAS External Signaling Bus .......................................................12
Figure 14.: T1/E1 Overhead Interface ............................................................................................................................. 12
Figure 15.: T1 External Overhead Datalink Bus .............................................................................................................. 13
Figure 16.: E1 Overhead External Datalink Bus .............................................................................................................. 13
Figure 17.: Simplified Block Diagram of the Framer Bypass Mode ................................................................................. 14
Figure 18.: T1 High-Speed Non-Multiplexed Interface .................................................................................................... 15
Figure 19.: E1 High-Speed Non-Multiplexed Interface .................................................................................................... 15
Figure 20.: Transmit High-Speed Bit Multiplexed Block Diagram .................................................................................... 16
Figure 21.: Receive High-Speed Bit Multiplexed Block Diagram ..................................................................................... 16
Figure 22.: Simplified Block Diagram of Local Analog Loopback .................................................................................... 17
Figure 23.: Simplified Block Diagram of Remote Loopback ............................................................................................ 17
Figure 24.: Simplified Block Diagram of Digital Loopback ............................................................................................... 18
Figure 25.: Simplified Block Diagram of Dual Loopback .................................................................................................. 18
Figure 26.: Simplified Block Diagram of the Framer Remote Line Loopback .................................................................. 19
Figure 27.: Simplified Block Diagram of the Framer Local Loopback .............................................................................. 19
Figure 28.: HDLC Controllers .......................................................................................................................................... 20
Figure 29.: Storing and Retrieving Message Contents .................................................................................................... 21
Figure 30.: Sending HDLC Messages ............................................................................................................................. 22
Figure 31.: Receiving HDLC Messages ........................................................................................................................... 23
Figure 32.: Receive HDLC Event Timing .........................................................................................................................24
Figure 33.: LAPD Frame Structure .................................................................................................................................. 27
Figure 34.: Block Diagram of the DS1 Transmit Overhead Input Interface of the XRT86VL3x ....................................... 33
Figure 35.: DS1 Transmit Overhead Input Interface Timing in ESF Framing Format mode ............................................ 35
Figure 36.: DS1 Transmit Overhead Input Timing in N or SLC96 Framing Format Mode ............................................ 36
Figure 37.: DS1 Transmit Overhead Input Interface module in T1DM Framing Format mode ........................................ 36
Figure 38.: Block Diagram of the DS1 Receive Overhead Output Interface of XRT86VL3x ...........................................37
Figure 39.: DS1 Receive Overhead Output Interface module in ESF framing format mode ...........................................39
Figure 40.: DS1 Receive Overhead Output Interface Timing in N or SLC96 Framing Format mode ........................... 40
Figure 41.: DS1 Receive Overhead Output Interface Timing in T1DM Framing Format mode ....................................... 41
Figure 42.: Block Diagram of the E1 Transmit Overhead Input Interface of XRT86VL3x ................................................42
Figure 43.: E1 Transmit Overhead Input Interface Timing ............................................................................................... 44
Figure 44.: Block Diagram of the E1 Receive Overhead Output Interface of XRT86VL3x .............................................. 45
Figure 45.: E1 Receive Overhead Output Interface Timing ............................................................................................. 46
Figure 46.: TAOS (Transmit All Ones) ............................................................................................................................. 47
Figure 47.: Simplified Block Diagram of the ATAOS Function ......................................................................................... 47
Figure 48.: Network Loop Up Code Generation .............................................................................................................. 48
Figure 49.: Network Loop Down Code Generation .......................................................................................................... 48
Figure 50.: Long Haul Line Build Out with -7.5dB Attenuation ........................................................................................ 49
Figure 51.: Long Haul Line Build Out with -15dB Attenuation ......................................................................................... 49
Figure 52.: Long Haul Line Build Out with -22.5dB Attenuation ...................................................................................... 50
Figure 53.: Arbitrary Pulse Segment Assignment ............................................................................................................ 51
Figure 54.: Typical Connection Diagram Using Internal Termination .............................................................................. 52
Figure 55.: Typical Connection Diagram Using Internal Termination .............................................................................53
Figure 56.: Simplified Block Diagram of the Equalizer and Peak Detector ......................................................................54
Figure 57.: Simplified Block Diagram of the Cable Loss Indicator ................................................................................... 54
Figure 58.: Test Configuration for Measuring Receive Sensitivity ................................................................................... 55
相關(guān)PDF資料
PDF描述
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VX38 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38_09 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VX38_0906 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38IB256 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VX38IB256ES 功能描述:界面開(kāi)發(fā)工具 Evaluation Board for XRT86VX38 256pin ICs RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類(lèi)型:RS-485 工具用于評(píng)估:ADM3485E 接口類(lèi)型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫(xiě)一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*