參數(shù)資料
型號： XRT86VL3X_07
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù)： 45/153頁
文件大?。?/td> 1316K
代理商： XRT86VL3X_07
XRT86VL3X
38
REV. 1.2.2
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
If the Receive Data Link Source Select bits of the Receive Data Link Select Register are set to 10, the Receive
Overhead Output Interface Block becomes Output source of the FDL bits.
The XRT86VL3x allows the user to select bandwidth of the Facility Data Link Channel in ESF framing format
mode. The FDL can be either a 4KHz or 2KHz data link channel. The Receive Data Link Bandwidth Select bits
of the Receive Data Link Select Register (RDLSR) determine the bandwidth of FDL channel in ESF framing
format mode.
The table below shows configuration of the Receive Data Link Bandwidth Select bits of the Receive Data Link
Select Register (TDLSR).
Figure 39
below shows the timing diagram of the Output and output signals associated with the DS1 Receive
Overhead Output Interface module in ESF framing format mode.
RECEIVE DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
1-0
Receive Data Link
Destination Select
R/W
00 - The extracted Facility Data Link bits are stored in either the LAPD con-
troller or the SLC96 buffer. At the same time, the extracted Facility Data
Link bits are outputted from the framer through the Receive Serial Data
Output Interface via the RxSer_n pins.
01 - The extracted Facility Data Link bits are outputted from the framer
through the Receive Serial Data Output Interface via the RxSer_n pins.
10 - The extracted Facility Data Link bits are outputted from the framer
through the Receive Overhead Output Interface via the RxOH_n pins. At
the same time, the extracted Facility Data Link bits are outputted from the
framer through the Receive Serial Data Output Interface via the RxSer_n
pins.
11 - The Facility Data Link bits are forced to one by the framer.
RECEIVE DATA LINK SELECT REGISTER (TDLSR) (ADDRESS = 0XN10AH)
B
IT
N
UMBER
B
IT
N
AME
B
IT
T
YPE
B
IT
D
ESCRIPTION
5-4
Receive Data Link
Bandwidth Select
R/W
00 - The Facility Data Link is a 4KHz channel. All available FDL bits (first
bit of every other frame) are used as data link bits.
01 - The Facility Data Link is a 2KHz channel. Only the odd FDL bits (first
bit of frame 1, 5, 9…) are used as data link bits.
10 - The Facility Data Link is a 2KHz channel. Only the even FDL bits (first
bit of frame 3, 7, 11…) are used as data link bits.
相關(guān)PDF資料
PDF描述
XRT86VL3X Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
XRT91L30_0611 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L306 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30IQ STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
XRT91L30 STS-12/STM-4 OR STS-3/STM-1 SONET/SDH TRANSCEIVER
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
XRT86VX38 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38_09 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
XRT86VX38_0906 制造商:EXAR 制造商全稱:EXAR 功能描述:OCTAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
XRT86VX38IB256 制造商:EXAR 制造商全稱:EXAR 功能描述:8-CHANNEL T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION
XRT86VX38IB256ES 功能描述:界面開發(fā)工具 Evaluation Board for XRT86VX38 256pin ICs RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*