• <ins id="qrl4f"></ins>
  • <thead id="qrl4f"><strike id="qrl4f"></strike></thead>
    參數(shù)資料
    型號(hào): XRT86VL32_2
    廠商: Exar Corporation
    元件分類(lèi): 通信及網(wǎng)絡(luò)
    英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    文件頁(yè)數(shù): 150/155頁(yè)
    文件大?。?/td> 814K
    代理商: XRT86VL32_2
    第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)當(dāng)前第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)
    XRT86VL32
    145
    DUAL T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
    REV. V1.2.0
    2
    RXMUTE
    R/W
    0
    Receive Output Mute:
    This bit permits the user to configure the Receive T1 Block to auto-
    matically pull its Recovered Data Output pins to GND anytime (and
    for the duration that) the Receive T1 LIU Block declares the LOS
    defect condition.
    In other words, if this feature is enabled, the Receive T1 LIU Block
    will automatically “mute” the Recovered data that is being routed to
    the Receive T1 Framer block anytime (and for the duration that) the
    Receive T1 LIU Block declares the LOS defect condition.
    0 – Disables the “Muting upon LOS” feature.
    1 – Enables the “Muting upon LOS” feature.
    N
    OTE
    :
    The receive clock is not muted when this feature is enabled.
    1
    EXLOS
    Extended LOS Enable:
    This bit allows users to extend the number of zeros at the receive
    input of each channel before RLOS is declared.
    When Extended LOS is enabled, the Receive T1 LIU Block will
    declare RLOS condition when it receives 4096 number of consecu-
    tive zeros at the receive input.
    When Extended LOS is disabled, the Receive T1 LIU Block will
    declare RLOS condition when it receives 175 number of consecu-
    tive zeros at the receive input.
    0 = Disables the Extended LOS Feature.
    1 = Enables the Extended LOS Feature.
    0
    ICT
    R/W
    0
    In-Circuit-Testing Enable:
    This bit allows users to tristate the output pins of all channels for in-
    circuit testing purposes.
    When In-Circuit-Testing is enabled, all output pins of the
    XRT86VL32 are “Tri-stated”. When In-Circuit-Testing is disabled, all
    output pins will resume to normal condition.
    0 = Disables the In-Circuit-Testing Feature.
    1 = Enables the In-Circuit-Testing Feature.
    T
    ABLE
    125: LIU G
    LOBAL
    C
    ONTROL
    R
    EGISTER
    2 (LIUGCR2) H
    EX
    A
    DDRESS
    : 0
    X
    0FE2
    B
    IT
    F
    UNCTION
    T
    YPE
    D
    EFAULT
    D
    ESCRIPTION
    -O
    PERATION
    7
    Force to "0"
    R/W
    0
    Set to "0"
    6
    RxTCNTL
    R/W
    0
    Receive Termination Select Control
    This bit sets the LIU to control the RxTSEL function with either the
    individual channel register bit or the global hardware pin.
    0 = Control of the receive termination is set to the register bits
    1 = Control of the receive termination is set to the hardware pin
    5-0
    Reserved
    R/W
    0
    This Bit Is Not Used
    T
    ABLE
    124: LIU G
    LOBAL
    C
    ONTROL
    R
    EGISTER
    1 (LIUGCR1) H
    EX
    A
    DDRESS
    : 0
    X
    0FE1
    B
    IT
    F
    UNCTION
    T
    YPE
    D
    EFAULT
    D
    ESCRIPTION
    -O
    PERATION
    相關(guān)PDF資料
    PDF描述
    XRT86VL32 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    XRT86VL32_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    XRT86VL32IB Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    XRT86VL34_07 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    XRT86VL34_1 Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    XRT86VL32ES 功能描述:網(wǎng)絡(luò)控制器與處理器 IC RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
    XRT86VL32IB 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 2 IND FULL DPLX FIFO TWO-FRAME, CAS, CCS RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
    XRT86VL32IB-F 功能描述:網(wǎng)絡(luò)控制器與處理器 IC 1-Ch T1/E1/J1 RoHS:否 制造商:Micrel 產(chǎn)品:Controller Area Network (CAN) 收發(fā)器數(shù)量: 數(shù)據(jù)速率: 電源電流(最大值):595 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:PBGA-400 封裝:Tray
    XRT86VL34 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - T1 REGISTER DESCRIPTION
    XRT86VL34_07 制造商:EXAR 制造商全稱(chēng):EXAR 功能描述:QUAD T1/E1/J1 FRAMER/LIU COMBO - E1 REGISTER DESCRIPTION