參數(shù)資料
型號(hào)： XRT86VL32_1
廠商： Exar Corporation
元件分類： 通信及網(wǎng)絡(luò)
英文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述： Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁(yè)數(shù)： 15/65頁(yè)
文件大?。?/td> 403K
代理商： XRT86VL32_1
XRT86VL32
12
REV. V1.2.0
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
TxCHN0_0/
TxSIG0
TxCHN2_0/
TxSIG2
B12
M18
I/O
8
Transmit Time Slot Octet Identifier Output 0 (TxCHNn_0) /
Transmit Serial Signaling Input (TxSIGn):
The exact function of these pins depends on whether or not the
transmit framer enables the transmit fractional/signaling interface,
as described below:
If transmit fractional/signaling interface is disabled -
TxCHNn_0:
These output pins (TxCHNn_4 through TxCHNn_0) reflect the
five-bit binary value of the current time slot being processed by the
transmit serial interface. Terminal Equipment can use the TxCH-
CLK to sample the five output pins of each channel in order to
identify the time slot being processed. This pin indicates the Least
Significant Bit (LSB) of the time slot channel being processed.
If transmit fractional/signaling interface is enabled - TxSIGn:
These pins can be used to input robbed-bit signaling data to be
inserted within an outbound DS1 frame or to input Channel Asso-
ciated Signaling (CAS) data within an outbound E1 frame, as
described below.
T1 Mode:
Signaling data (A,B,C,D) of each channel must be pro-
vided on bit 4,5,6,7 of each time slot on the TxSIG pin if 16-code
signaling is used. If 4-code signaling is selected, signaling data
(A,B) of each channel must be provided on bit 4, 5 of each time
slot on the TxSIG pin. If 2-code signaling is selected, signaling
data (A) of each channel must be provided on bit 4 of each time
slot on the TxSIG pin.
E1 Mode:
Signaling data in E1 mode can be provided on the
TxSIGn pins on a time-slot-basis as in T1 mode, or it can be pro-
vided on time slot 16 only via the TxSIGn input pins. In the latter
case, signaling data (A,B,C,D) of channel 1 and channel 17 must
be inserted on the TxSIGn pin during time slot 16 of frame 1, sig-
naling data (A,B,C,D) of channel 2 and channel 18 must be
inserted on the TxSIGn pin during time slot 16 of frame 2...etc.
The CAS multiframe Alignments bits (0000 bits) and the extra bits/
alarm bit (xyxx) must be inserted on the TxSIGn pin during time
slot 16 of frame 0.
N
OTE
:
Transmit fractional interface can be enabled by
programming to bit 4 - TxFr1544/TxFr2048 bit from
register 0xn120 to ‘1’.
N
OTE
:
These 8 pins are internally pulled “Low” for each channel.
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
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M
A)
D
ESCRIPTION
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