參數(shù)資料
型號: XRT86VL32_1
廠商: Exar Corporation
元件分類: 通信及網(wǎng)絡(luò)
英文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
中文描述: Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0
文件頁數(shù): 10/65頁
文件大?。?/td> 403K
代理商: XRT86VL32_1
XRT86VL32
7
DUAL T1/E1/J1 FRAMER/LIU COMBO - HARDWARE DESCRIPTION
REV. V1.2.0
TRANSMIT SYSTEM SIDE INTERFACE
S
IGNAL
N
AME
B
ALL
#
T
YPE
O
UTPUT
D
RIVE
(
M
A)
D
ESCRIPTION
TxSER0/
TxPOS0
TxSER2/
TxPOS2
D11
L18
I
-
Transmit Serial Data Input (TxSERn)/Transmit Positive Digital
Input (TxPOSn):
The exact function of these pins depends on the mode of opera-
tion selected, as described below.
DS1/E1 Mode - TxSERn
These pins function as the transmit serial data input on the system
side interface, which are latched on the rising edge of the TxSER-
CLKn pin. Any payload data applied to this pin will be inserted into
an outbound DS1/E1 frame and output to the line. In DS1 mode,
the framing alignment bits, facility data link bits, CRC-6 bits, and
signaling information can also be inserted from this input pin if
configured appropriately. In E1 mode, all data intended to be
transported via Time Slots 1 through 15 and Time slots 17 through
31 must be applied to this input pin. Data intended for Time Slots 0
and 16 can also be applied to this input pin If configured accord-
ingly.
DS1 or E1 High-Speed Multiplexed Mode* - TxSERn
In this mode, these pins are used as the high-speed multiplexed
data input pin on the system side. High-speed multiplexed data of
channels 0-3 must be applied to TxSER0 in a byte or bit-inter-
leaved way. The framer latches in the multiplexed data on
TxSER0 using TxMSYNC/TxINCLK and demultiplexes this data
into 4 serial streams. The LIU block will then output the data to the
line interface using TxSERCLKn.
DS1 or E1 Framer Bypass Mode - TxPOSn
In this mode, TxSERn is used for the positive digital input pin
(TxPOSn) to the LIU.
N
OTE
:
1.
*High-speed multiplexed modes include (For T1/E1)
16.384MHz HMVIP, H.100, Bit-multiplexed modes, and
(For T1 only) 12.352MHz Bit-multiplexed mode.
2.
In DS1 high-speed modes, the DS-0 data is mapped into
an E1 frame by ignoring every fourth time slot (don’t
care).
3.
These 8 pins are internally pulled “High” for each
channel.
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